Abstract: A wire interconnect structure of an integrated circuit includes a first wiring layer, a second wiring layer, a third wiring layer, first conductive via structures, second conductive via structures, and third conductive via structures. The first wiring layer includes a first wire connected to first transistors and a second wire connected to second transistors. The second wiring layer includes third wires and fourth wires that are perpendicular to the first wire and the second wire. The third wiring layer includes a fifth wire and a sixth wire that are parallel to the first wire and the second wire and respectively connected to a first contact pad and a second contact pad above. The first transistors are electrically connected to the first contact pad through the first wire, and the second transistors are electrically connected to the second contact pad through the second wire.

Abstract: A video decoding method and a video decoding device are provided, and the video decoding method includes the following steps. A to-be-decoded bin string is received. A plurality of first current syntax elements in the to-be-decoded bin string are decoded based on a first context model until a decoding output value of the last one of the first current syntax elements matches a specific bin pattern. When the first current syntax elements are decoded, in response to that a state machine is switched from a first decoding operation mode to a second decoding operation mode, a second current syntax element that exists based on the last one of the first current syntax elements is decoded.

Abstract: A projection apparatus and a keystone correction method thereof are provided. The projection apparatus includes a display processing circuit including an image processing circuit, a first keystone correction circuit, a rotation circuit, a second keystone correction circuit, and a video output circuit. The first keystone correction circuit performs first keystone correction processing on a processed image frame based on horizontal scaling processing to obtain a first corrected image frame. The rotation circuit performs rotation processing on the first corrected image frame to write a rotated image frame into a memory. The second keystone correction circuit reads the rotated image frame from the memory and performs second keystone correction processing on the rotated image frame based on the horizontal scaling processing to obtain a second corrected image frame. The video output circuit transmits the second corrected image frame to a projection module through a data transmission interface.

Abstract: Disclosed are a trapped state detection method and a mobile platform. The trapped state detection method is applied to the mobile platform including an actuator, and includes: selectively acquiring first signal characteristic or second signal characteristic in an external environment in a process in which the actuator drives the mobile platform to move; determining whether an abnormality occurs according to the first signal characteristic acquired in a first default time interval; controlling the actuator to perform a default verification behavior to change a position or a posture of the mobile platform when an occurrence of the abnormality is determined; determining whether another abnormality occurs according to the first signal characteristic or the second signal characteristic acquired in a second default time interval after the actuator performs the default verification behavior; and confirming that the mobile platform is in a trapped state when an occurrence of the another abnormality is determined.

Abstract: An image processing device and an image processing method are provided. A frame divider divides an original frame into a plurality of divided blocks. A multi-core circuit coupled to the frame divider and includes a plurality of processing cores and a frame stitching circuit. The processing cores perform an image processing process on the divided blocks to generate a plurality of processed frame blocks. The frame stitching circuit performs an image stitching process according to the processed frame blocks to generate a processed frame. The processing cores fetch the divided blocks and a plurality of extension pixels extending from the divided blocks to perform the image processing process, and a column number of the extension pixels is configured according to a window size requested by at least one window algorithm of the image processing process.

Abstract: Disclosed are a method for simultaneous localization and mapping and a mobile platform using the same. The method for simultaneous localization and mapping is applied to the mobile platform, and includes: continuously collecting and storing odometer data and environment sensing data of the mobile platform when the mobile platform moves based on a motion trajectory; combining a certain amount of the odometer data and the environmental sensing data to obtain environmental information whenever the certain amount of odometer data and environmental sensing data is reached and stored; performing a simultaneous localization and mapping procedure according to a current map and the odometer data and environmental information continuously obtained; repeating the above steps until the mobile platform completes the motion according to the motion trajectory. Therefore, the mobile platform can synthesize the environmental information similar to sensing data of the lidar while moving without installing a high-cost lidar.

Abstract: A video decoding and display system and a memory accessing method thereof are provided. The video decoding and display system includes a plurality of memories, a plurality of display processing cores, a plurality of decoding processing cores, and a mapping circuit. The memories are configured to record a plurality of frame segments of a vide frame. The decoding processing cores decode the frame segments in parallel. The mapping circuit is coupled between the decoding processing cores and the memories. Each of the memories correspondingly records one of the frame segments. Each of the display processing cores correspondingly accesses one of the memories. Each of the decoding processing cores accesses the memories through the mapping circuit, and the decoding processing cores access one of the memories in order.

Abstract: An electronic device includes a core circuit and a detecting circuit. The core circuit receives a first clock signal and a second clock signal that are different. The core circuit generates a first working state and a second working state respectively according to the first clock signal and the second clock signal. The detecting circuit detects a relationship between the first working state and the second working state to generate a reset signal. The reset signal is configured to reset the relationship between the first working state and the second working state to an initial corresponding relationship, and reduce an influence of electromagnetic interference on the electronic device.

Abstract: A phase interpolator capable of preventing a glitch from being generated during a clock signal switching operation and a clock signal selector thereof are provided. The clock signal selector includes a selector and a selection signal generator. The selector receives multiple clock signals with different phases. The selector selects one of the clock signals according to a selection signal to generate a selected clock signal. The selection signal generator is coupled to the selector and generates the selection signal. When the selector switches from selecting a first clock signal to selecting a second clock signal as the selected clock signal, the selection signal generator generates a set time point according to a transition point of one of the first clock signal and the second clock signal whose phase lags behind a phase of the other, and generates the selection signal according to the set time point.

Abstract: A deskew circuit for a differential signal is provided. A first common mode voltage generating circuit generates a first common mode voltage signal according to first and second differential input signals. A voltage buffer circuit is coupled to the first common mode voltage generating circuit and has an input impedance higher than a preset value, and buffers the first common mode voltage signal and the first and second differential input signals to generate a second common mode voltage signal, a third differential input signal, and a fourth differential input signal. A second common mode voltage generating circuit is coupled to the voltage buffer circuit and generates a third common mode voltage signal according to the third and fourth differential input signals. An output circuit generates a deskew output signal according to the third and fourth differential input signals and the second and third common mode voltage signals.

Abstract: A signal receiver and a signal transceiver are provided, which may avoid unnecessary leakage current. The signal receiver includes a termination switch pair, a first resistor, a second resistor, and a pull-down circuit. The termination switch pair receives an operation power supply. The termination switch pair has a common control end. The first resistor is coupled between a first signal input end and the common control end. The second resistor is coupled between a second signal input end and the common control end. The pull-down circuit is coupled between the common control end and a reference voltage end. The pull-down circuit determines whether to pull down a first control voltage on the common control end to a reference voltage according to a power-on state or a power-off state of the signal receiver.

Abstract: Provided is a layout structure adapted for a signal format converter. The layout structure includes a first and a second capacitor array. The first capacitor array is disposed on one side of a reference axis, and includes multiple first capacitor units that form multiple first capacitors. The first capacitors respectively have multiple first capacitances. The second capacitor array is disposed on the other side of the reference axis, and includes multiple second capacitor units that form multiple second capacitors. The second capacitors respectively have multiple second capacitances. The first capacitors respectively correspond to the second capacitors. Each first capacitor and each corresponding second capacitor are symmetrical with respect to the reference axis, or each first capacitor and each corresponding second capacitor are separated from each other by the same distance. Each first capacitor and each corresponding second capacitor have the same capacitance.

Abstract: A voltage regulating device and a mode switching detecting circuit are provided. The mode switching detecting circuit is configured to reset a soft start circuit of the voltage regulating device. The mode switching detecting circuit includes a mode switching signal detector, a reset signal generator, and a reset status detector. The mode switching signal detector receives a mode switching signal and generates a setting signal according to a transition edge of the mode switching signal. The reset signal generator is coupled to the mode switching signal detector and generates a reset activating signal according to the setting signal. The reset activating signal drives the soft start circuit to perform a reset operation. The reset status detector compares an output voltage of the soft start circuit and a reference voltage to generate a clear signal. The reset signal generator clears the reset activating signal according to the clear signal.

Abstract: A voltage regulator, including an amplifier, a voltage setting circuit and a power transistor, is provided. The amplifier includes a first current source and a second current source. The amplifier has two input terminals to respectively receive a reference voltage and a feedback voltage. The first current source is coupled between the operating power source and an output terminal of the amplifier, and provides a first current to the output terminal. The second current source is coupled between the output terminal and a reference ground terminal, and draws a second current from the output terminal. The voltage setting circuit is coupled to the output terminal, and increases a driving voltage on the output terminal according to the first current in a voltage bypass mode. The power transistor receives the driving voltage and generates an output voltage according to the driving voltage based on the operating power source.

Abstract: The disclosure provides a bias voltage calibration circuit adapted for a signal receiving device. The bias voltage calibration circuit includes a reference voltage generator, a voltage-current converter, and a bias current generator. The reference voltage generator receives a voltage adjustment signal, and adjusts a voltage value of a generated reference voltage according to the voltage adjustment signal. The voltage-current converter is coupled to the reference voltage generator, and converts the reference voltage to generate a reference current. The bias current generator generates a plurality of bias currents according to the reference current, and provides the bias current to an equalization circuit of the signal receiving device in a calibration mode.

Abstract: A voltage regulator including an amplifier, a start signal generator and a power transistor is provided. The amplifier has a first positive input terminal, a second positive input terminal, and a negative input terminal to receive a start signal, a reference voltage and a feedback voltage respectively. An output terminal of the amplifier generates a driving voltage. The start signal generator is coupled to the first positive input terminal of the amplifier and generates the start signal, which is incremental, during a startup time interval in a voltage bypass mode. The power transistor generates an output voltage according to the driving voltage based on an operating power. In the voltage bypass mode, the reference voltage is equal to the operating power. A soft-start effect can be effectively achieved by the voltage regulator in the voltage bypass mode.

Abstract: The disclosure provides a voltage regulator with a soft-start effect. The voltage regulator includes an amplifier, a first voltage setting circuit, a voltage selector and a power transistor. The amplifier has two input terminals to receive respectively a reference voltage and a feedback voltage. The amplifier has a current source to provide a current to an output terminal. In a voltage bypass mode, the first voltage setting circuit increases a driving voltage on the output terminal according to the current based on a selection voltage. In the voltage bypass mode, the voltage selector sequentially reduces the selection voltage respectively in multiple time intervals in a startup time interval. The power transistor receives the driving voltage, and generates an output voltage according to the driving voltage based on an operating power supply.

Abstract: A projection device and a keystone correction method thereof are provided. The keystone correction method is adapted for the projection device and includes the following steps. A first image is obtained. A first line-taking position parameter is determined according to a ratio of a first target edge length to a second target edge length. At least one line of input pixels disposed in a first direction is retrieved from the first image according to the first line-taking position parameter. A first scaling process related to the first direction is performed according to at least one line of input pixels of the first image, such that a line of output pixels of a second image disposed in the first direction is generated. The projection device projects the second image onto a projection screen to display a rectangular projected image.

Abstract: A projection device and a projection image correction method are provided. Four target coordinates of four target vertices forming a target quadrilateral boundary are obtained. A first trapezoidal boundary is obtained according to a predetermined image boundary and a first coordinate component of each of the four target coordinates. At least one edge of the target quadrilateral boundary is extended until intersecting with at least one of two reference line segments to obtain a second trapezoidal boundary. Bases of the first trapezoidal boundary are perpendicular to bases of the second trapezoidal boundary. First direction scaling processing is performed according to the first trapezoidal boundary, and second direction scaling processing is performed according to the second trapezoidal boundary, to scale an original image into a target image block aligned with the target quadrilateral boundary in an output image. The projection device projects the output image to display a rectangular projection image.

Abstract: A projection device and a projection picture correction method thereof are provided. When the projection device performs projection toward a projection surface, a plurality of target coordinates of a plurality of target vertexes are obtained based on a plurality of planes of the projection surface. The plurality of planes are not coplanar with each other, and the plurality of target vertexes form a target polygon. A first direction scaling process is performed respectively on a plurality of first image portions of an original trapezoidal image and a trapezoidal image block is generated. A second direction scaling process is performed respectively on a plurality of second image portions of the trapezoidal image block and a target image block aligned with the target polygon is generated. An output image including the target image block is projected onto the projection surface.