Patents Assigned to Allegro Microsystems, LLC
  • Patent number: 12681053
    Abstract: A sensor integrated circuit includes a sensing circuit configured to generate the sensor output signal and a fault circuit to detect a fault and generate a fault signal indicative of the fault. A combined signal indicative of the fault signal when a fault is detected and indicative of a reference voltage associated with the sensor IC at other times is provided at a shared connection of the sensor IC. Embodiments include a current sensor IC and fault detectors configured to detect one or more faults.
    Type: Grant
    Filed: February 2, 2024
    Date of Patent: July 14, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventors: Matthew Hein, Benjamin Damkroger
  • Patent number: 12685188
    Abstract: An integrated circuit package having more than one semiconductor die includes a spark gap to provide a current path designed to protect the device. The spark gap can be provided between an exposed portion of a corner lead and an exposed portion of a tie bar and/or between exposed portions of adjacent leads. The spark gap distance is designed to achieve required ratings for a given application. Stacked and side-by-side die configurations are described.
    Type: Grant
    Filed: February 1, 2024
    Date of Patent: July 14, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventors: Washington Lamar, Weidong Wang, Maxim Klebanov, Sagar Saxena, Yash Shaileshbhai Patel
  • Patent number: 12683602
    Abstract: A drive circuit comprises a transformer, a primary side circuit communicating with a primary winding of the transformer, and a secondary side circuit communicating with a secondary winding of the transformer. The primary side circuit couples to a primary side supply voltage and to an input signal and couples a first signal to the primary winding. The secondary side circuit communicates with the semiconductor switch and provides, responsive to the first signal, a second signal to control the semiconductor switch, comprising at least one of a primary bias and a secondary bias. For a first gate charge level range, the secondary side circuit provides the primary bias. For a second gate charge level range greater than the first range, the secondary side circuit is controlled by a secondary bias circuit comprising a storage capacitor configured to accumulate voltage when the secondary side circuit is providing the primary bias.
    Type: Grant
    Filed: August 23, 2024
    Date of Patent: July 14, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventors: Vijay Mangtani, Maurizio Salato
  • Patent number: 12681110
    Abstract: A system, comprising: a reference magnetic field source that is configured to generate a reference magnetic field; a plurality of magnetic field sensing elements arranged in a sensing bridge, the sensing bridge being configured to sense the reference magnetic field and an external magnetic field simultaneously, the sensing bridge being configured to output a first signal and a second signal; a first circuit that is configured to generate a common mode signal of the sensing bridge based on the first signal and the second signal; an adjustment circuit that is configured to adjust a sensitivity of the sensing bridge based, at least in part, on a common mode signal of the sensing bridge; and a processing circuitry that is configured to use a differential signal of the sensing bridge to generate an output signal, the differential signal being based on a strength of the external magnetic field.
    Type: Grant
    Filed: August 30, 2023
    Date of Patent: July 14, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventor: Hernán D. Romero
  • Patent number: 12674813
    Abstract: A speed sensor device includes sensing elements to sense an angle of a moving target and to generate sine and cosine signals in response thereto; a signal condition circuit to process the sine and cosine signals, the processed sine and cosine signals having a phase lag introduced by the signal condition circuit; and a phase lead filter to receive the processed sine and cosine signals and to reduce the phase lag in the processed sine and cosine signals.
    Type: Grant
    Filed: June 25, 2024
    Date of Patent: July 7, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventors: Pedro Julian, Alfredo A. Falcón
  • Patent number: 12676611
    Abstract: Magnetic sensing device integrated in a magnetic switch device that makes or breaks contact in the presence of an external magnetic field, comprising: a first transistor biased at a first terminal by a first bias voltage and a first magnetoresistive element having a first resistance variable with the external magnetic field. At a reference field strength, the first resistance has a first reference resistance value, and the first bias voltage is adjustable to control a first current at the second terminal of the first transistor at a first reference current value. When the external magnetic field is varied around the reference field strength, the first variable resistance varies around the first reference resistance value by a resistance delta, such that the first current modulates around the first reference current value by a current delta. A magnetic switch device comprising the magnetic sensing device is also disclosed.
    Type: Grant
    Filed: January 31, 2024
    Date of Patent: July 7, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventors: Hakan Ates Gurcan, Jeffrey Childress
  • Publication number: 20260186079
    Abstract: A magnetic field sensor includes magnetoresistance elements supported by a surface of the die defining a plane, and a concentrator layer over the surface of the die and having an aperture. A first magnetoresistance element is adjacent to a first edge of the aperture and has a first reference direction parallel to the surface of the die and substantially perpendicular to the first aperture edge and a second magnetoresistance element is adjacent to a second edge of the aperture and has the first reference direction. The concentrator layer redirects the applied magnetic field to present a differential field parallel to the plane of the die to the magnetoresistance elements in response to applied field perpendicular to the plane of the die and to present a reduced magnitude and common mode field to the magnetoresistance elements in response to the applied field parallel to the plane of the die.
    Type: Application
    Filed: February 24, 2026
    Publication date: July 2, 2026
    Applicant: Allegro MicroSystems, LLC
    Inventors: Rémy Lassalle-Balier, Alexander Latham
  • Publication number: 20260186081
    Abstract: A sensor comprising: a sensing bridge including a first leg and a second leg, the first leg including a first magnetoresistance (MR) element that is coupled to a second MR element via a first transistor, the second leg including a third MR element that is coupled to a fourth MR element via a second transistor; a frontend circuit having a first input and a second input, the first input being coupled to the first leg, and the second input being coupled to the second leg; and a first resistive digital-to-analog converter (R-DAC) that is coupled to at least the first leg, the first R-DAC being arranged to receive a first trim code and modify a first resistance of the first leg based on the first trim code.
    Type: Application
    Filed: December 27, 2024
    Publication date: July 2, 2026
    Applicant: Allegro MicroSystems, LLC
    Inventors: Leandro Fuentes, Javier Cuneo, Bruno Luis Uberti, Manuel Rivas
  • Patent number: 12671333
    Abstract: A device includes a signal generator configured to generate signals to control first and second switches coupled in a first half-bridge DC-DC converter configuration, the first and second switches being configured in a buck mode of operation or in a boost mode of operation.
    Type: Grant
    Filed: March 27, 2024
    Date of Patent: June 30, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventors: Alessandro Montanelli, Alessandro Bacceli, Marco Cignoli
  • Patent number: 12669320
    Abstract: A redundant inductive sensor system includes at least two interface circuits, each associated with a respective transmitting coil that is electromagnetically coupled to one or more receiving coils. The first interface circuit transmits during a first transmitting interval and the second interface circuit transmits during a second transmitting interval that does not overlap with the first transmitting interval. The first interface circuit receives the second signal during a first listening interval of the first interface circuit encompassing the second transmitting interval and the second interface circuit receives the first signal during a second listening interval of the second interface circuit encompassing the first transmitting interval. By listening to transmissions from transmitting coils other than an associated transmitting coil, interface circuits can detect errors in other interface circuits.
    Type: Grant
    Filed: August 14, 2024
    Date of Patent: June 30, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventors: Philippe Tekieli, Solène Bastien
  • Patent number: 12672551
    Abstract: Aspects of the present disclosure include systems, structures, integrated circuit (IC) packages or modules, circuits, and methods providing a transformer with first and second coils and a sense coil configured adjacent to and closely coupled with the second coil. The circuits, ICs and IC packages and modules may include various types of circuits. In some examples, IC packages or modules may include a galvanically-isolated gate driver or other high voltage circuit.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: June 30, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventors: John Horan, Paddy Collins
  • Patent number: 12672592
    Abstract: A current sensor integrated circuit (IC) package includes an insulation structure disposed between a semiconductor die and a lead frame to control gap height and prevent the die from tilting and dropping the magnetic field coupling between the die the primary conductor. An insulation structure is disposed between the die and the lead frame such that the die remains level and magnetic coupling remains intact. An insulation structure may control the gap height between the lead frame and the die evenly during transfer molding, by supporting the die across its length and/or width. Epoxy dots are also or instead used to control the gap height and eliminate die tilt.
    Type: Grant
    Filed: February 22, 2024
    Date of Patent: June 30, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventors: David Youm, Weidong Wang, Natasha Healey
  • Patent number: 12669559
    Abstract: Methods and apparatus for an MR device having a ferromagnetic material, a heavy metal layer configured to flow a charge current, and an insulating layer between the ferromagnetic material and the heavy metal layer. The insulating layer is configured to electrically insulate and to magnetically couple the heavy metal layer and the ferromagnetic layer for generating a field like (FL) field in the ferromagnetic material in response to the charge current. In some embodiments, the MR device comprises a TMR device having a free layer or a reference layer oriented by the charge current. In other embodiments, the MR device comprises a GMR device.
    Type: Grant
    Filed: September 20, 2023
    Date of Patent: June 30, 2026
    Assignees: Allegro MicroSystems, LLC, Commissariat à l'énergir atomique et aux énergies alternatives
    Inventors: Aurélie Solignac, Myriam Pannetier-Lecoeur, Claude Fermon, Paolo Campiglio, Jean-Michel Daga
  • Publication number: 20260177590
    Abstract: A sensor, including: a gradiometer including a plurality of magnetoresistors, the gradiometer being configured to generate a sensing signal in response to a magnetic field that is at least in part produced as a result of an electrical current flowing through a conductor; and electronic circuitry configured to detect an electrical current consumption of the gradiometer, compare the electrical current consumption against at least one of a first threshold and a second threshold, and output an indication that the sensor is subject to tampering based on an outcome of the comparison.
    Type: Application
    Filed: December 20, 2024
    Publication date: June 25, 2026
    Applicant: Allegro MicroSystems, LLC
    Inventors: Yannick Vuillermet, Alexander Latham, Rémy Lassalle-Balier, Conrado Rossi
  • Patent number: 12666643
    Abstract: According to one aspect of the present disclosure, a semiconductor device includes a substrate having a first type dopant. In some embodiments, the semiconductor device also includes an epitaxial layer above the substrate, having a second type dopant and a top region. In some embodiments, the semiconductor device also includes a trench in the top region of the epitaxial layer; at least one doped ring implanted in the epitaxial layer below the trench; and a dielectric material filling within the trench. In some embodiments, there is a twelve-sided body tie in the epitaxial layer, wherein the sides of the twelve-sided body tie are not all equal to each other.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: June 23, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventors: Yu-Chun Li, Thomas S. Chung, Maxim Klebanov, Chung C. Kuo, James M. McClay, Robert A. Wilson
  • Patent number: 12665613
    Abstract: A signal encoding and decoding protocol to transmit both clock information and a data payload in a single line is disclosed. Data may be encoded in a unipolar non-return-to-zero line in which an initial pulse width determines a clock frequency, followed by a series of pulses indicating the data payload. Each clock transition following an initial synchronization pulse indicates a data bit in which the value of the bit is determined in relation to the previous bit. Edge information may indicate a change in bit value from the previous bit. If the transmission signal remains at the same level for a subsequent clock period, the bit value remains the same.
    Type: Grant
    Filed: May 13, 2024
    Date of Patent: June 23, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventors: Ahmad Nour Halawani, Emil Pavlov
  • Patent number: 12665483
    Abstract: Systems, circuits, and methods provide heat-sink-coupled conductive structures having eddy current mitigation structures, formed as S-notches, and integrated current sensors. An example conductive structure includes a high-current conductor structure having a main current path including an S-notch portion configured to mitigate eddy currents. The structure includes a low-current conductor structure connected to a first heat sink and having a main current path configured to conduct a second current. A differential current sensor is connected to the low-current conductor structure and configured to detect current flowing in the high-current conductor structure. A power module includes the conductive structure and a power converter that is configured to convert power between the first current in the high-current conductor structure and the second current in the low-current conductor structure. The conductive structures and power modules can be used for EV applications.
    Type: Grant
    Filed: March 15, 2024
    Date of Patent: June 23, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventors: Christian Kasparek, Simon E. Rock
  • Patent number: 12656415
    Abstract: Systems, circuits, and methods provide core-based closed-loop current sensors utilizing a coil connected to an IC having a magnetic field sensor configured to measure current in one or more conductors such as busbars. A closed-loop current sensor includes a magnetic core having first and second ends separated by a gap and an aperture receiving the one or more conductors; a magnetic field sensor disposed on a substrate and integrated in an IC is disposed in the gap, where the magnetic field sensor is configured to receive magnetic flux from the gap, where the IC is configured to measure AC current in the one or more conductors; and a coil integrated with the substrate and coupled to the IC, wherein the coil is configured to provide negative magnetic feedback for closed-loop compensation.
    Type: Grant
    Filed: March 15, 2024
    Date of Patent: June 16, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventors: Emil Pavlov, Simon E. Rock
  • Patent number: 12656420
    Abstract: Method and apparatus for a 3D sensor having die Hall element clusters located on first and second die. In an embodiment, a sensor IC package includes a first die having first, second, and third Hall clusters having different axes of magnetic field sensitivity and a second die having a fourth Hall cluster having sensitivity in the first and third axes of sensitivity. The sensor provides 3D field sensing for stroke, end of shaft and side shaft sensing applications.
    Type: Grant
    Filed: May 14, 2024
    Date of Patent: June 16, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventors: Ahmad Nour Halawani, Emil Pavlov, Lorena Perdigon Toro, Sarkis Dono
  • Patent number: 12651691
    Abstract: Aspects of the present disclosure include systems, structures, circuits, and methods providing planar transformers and planar transformer structures. The planar transformers and transformer structures can include first and second core layers of soft ferromagnetic material on opposite sides of an electrical substrate. First and second coils can be configured as conductive traces disposed on the opposite sides of the substrate. The first and second soft ferromagnetic layers are in contact in a contact region. One or more holes are disposed in either or both of the soft ferromagnetic layers and contain soft ferromagnetic material to reduce reluctance of the transformer structure. The planar transformer can be included in integrated circuit (chip) packages or modules. The packages and modules may include various types of circuits; in some examples, chip packages or modules may include a gate driver or other high voltage circuit.
    Type: Grant
    Filed: July 11, 2023
    Date of Patent: June 9, 2026
    Assignee: Allegro MicroSystems, LLC
    Inventor: William P. Taylor