Patents Assigned to Allegro Microsystems, LLC
  • Patent number: 12000870
    Abstract: In one aspect, a sensor includes a first metal layer portion and a second metal layer portion separated by an insulator material; a conductive material layer in electrical contact with the first metal layer portion and the second metal layer portion; and a tunnel magnetoresistance (TMR) element positioned on and in electrical contact with the conductive material layer. A first current is configured to flow from the first metal layer portion, through the conductive material layer, to the second metal layer portion, and a second current is configured to flow from the first metal layer portion, through the conductive material layer, through the TMR element, and exiting through a top of the TMR element.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: June 4, 2024
    Assignee: Allegro MicroSystems, LLC
    Inventors: Samridh Jaiswal, Paolo Campiglio, Sundar Chetlur, Maxim Klebanov, Yen Ting Liu
  • Publication number: 20240176405
    Abstract: An interface circuit, comprising: I/O circuitry configured to couple one or more first terminals with one or more second terminals; a voltage regulator configured to power the I/O circuitry; a restrictor element that is disposed between the voltage regulator and the I/O circuitry, the restrictor element being disposed on a circuit path that connects the voltage regulator to the I/O circuitry, the restrictor element being configured to open the circuit path and disconnect the voltage regulator from the I/O circuitry when an electrical current that is being supplied to the I/O circuitry exceeds a threshold; and a voltage suppressor that is disposed on the circuit path that connects the voltage regulator to the I/O circuitry, the voltage suppressor being disposed between the restrictor element and the I/O circuitry, the voltage suppressor being configured to limit, to a first voltage value, a voltage that is input into the I/O circuitry.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventors: Christy Looby, Colin Hall, James McIntosh
  • Publication number: 20240175947
    Abstract: Magnetic field sensors having at least two bridges including MR elements are described. MR elements of each bridge have different magnetic reference directions. A first bridge is positioned to sense a first uniform magnetic field of a first polarity and a second bridge is positioned to sense a second uniform magnetic field of a second polarity opposite to the first polarity. The first and second uniform magnetic fields make up a differential field of interest. The described magnetic field sensors sense the field of interest in a manner that is immune to stray fields. Dual signal path embodiments are described in which outputs of the two bridges are independently processed and single signal path embodiments include a single signal path for processing the output of a combined (e.g., parallel) bridge arrangement.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventor: Hernán D. Romero
  • Patent number: 11994541
    Abstract: A current sensor assembly can include: a coil structure having a first coil and a second coil connected in series, the coil structure configured to generate a differential magnetic field responsive to an electrical current passing through the first and second coils; a first magnetic field sensing element disposed proximate to the first coil and operable to generate a first signal responsive to the differential magnetic field passing through the first magnetic field sensing element in a first direction; a second magnetic field sensing element disposed proximate to the second coil and operable to generate a second signal responsive to the differential magnetic field passing through the second magnetic field sensing element in a second direction; and a circuit operable to subtract the first and second signals to generate a differential signal proportional to the electrical current.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: May 28, 2024
    Assignee: Allegro MicroSystems, LLC
    Inventors: Loïc André Messier, Yannick Vuillermet, Andreas P. Friedrich
  • Publication number: 20240168108
    Abstract: A magnetoresistive element has a tunnel barrier layer included between a ferromagnetic reference layer having a fixed reference magnetization and a ferromagnetic sense layer having a free sense magnetization. The sense magnetization has a ferromagnetic material composition and a stable vortex configuration in the absence of an applied magnetic field. The ferromagnetic material composition varies across the thickness of the sense layer from a composition with higher magnetization near the tunnel barrier layer to a composition with lower magnetization away from the tunnel barrier layer, such that the sense magnetization and ferromagnetic exchange strength of the sense layer are higher near the tunnel barrier layer than away from the tunnel barrier layer.
    Type: Application
    Filed: March 15, 2022
    Publication date: May 23, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventors: Jeffrey Childress, Andrey Timopheev
  • Publication number: 20240168104
    Abstract: A method for use in a magnetic field sensor, including: in each of a plurality of calibration periods, generating a reference magnetic field based on a different one of a plurality of drive codes; storing, in a memory, a plurality of values of a reference magnetic field signal that is generated in response to the reference magnetic field, each of the values of the reference magnetic field signal being generated by sampling the reference magnetic field signal in a different one of the plurality of calibration periods; calculating a calibration gain coefficient based on the plurality of values of the reference magnetic field signal; and storing the calibration gain coefficient in the memory and using the calibration gain coefficient to adjust an output of the magnetic field sensor.
    Type: Application
    Filed: November 18, 2022
    Publication date: May 23, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventors: Arun Prasad Javvaji, Craig S. Petrie
  • Publication number: 20240170478
    Abstract: In one aspect, a semiconductor device includes a first region, a second region and a trench separating the first and the second regions. The trench includes a trench liner that includes a dielectric, and a semiconductor material surrounded by the trench liner. The first region includes a first buried layer implanted in a substrate, a first stack of layers that includes a first middle layer located above the first buried layer, a first well located on and in contact with the first middle layer and a second well in contact with the first well. The second region includes a second stack of layers. In response to a voltage difference between the first and the second regions exceeding a threshold voltage, a conduction current is formed. A distance of the first stack of layers to the trench controls the conduction current to activate a transistor to function as a voltage clamp.
    Type: Application
    Filed: November 23, 2022
    Publication date: May 23, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventors: Chung C. Kuo, Maxim Klebanov, James McClay, Sagar Saxena
  • Publication number: 20240151751
    Abstract: Output buffer diagnostic circuits for monitoring a sensor output buffer include a duplicate resistive network corresponding to a resistive network in the monitored sensor output buffer. The duplicate resistive network may include the same or similar topology as the output buffer resistive network. The duplicate resistive network is configured to produce a differential duplicate signal indicative of when an error condition exits in the sensor output buffer. The diagnostic circuit can include averaging circuitry configured to receive the differential duplicate signal and produce an average duplicate signal. The diagnostic circuit can include an error comparison circuit configured to receive the average duplicate signal and detect when the average duplicate signal exceeds a nominal or preset error value corresponding to an error condition in the sensor output buffer. The error comparison circuit is configured to produce an error indication when the average duplicate signal exceeds the preset error value.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventors: Matthieu THOMAS, Radek ZEIPL, Petr BILY
  • Publication number: 20240146196
    Abstract: An adaptive current limit circuit is provided in a power converter to achieve a fixed output current limit over duty cycle. In a converter including a high side switch, a low side switch coupled to the high side switch at a switch node, and an inductor coupled between an input voltage source and the switch node, the adaptive current limit circuit is coupled to receive the high side control signal and configured to generate an adaptive current limit threshold that varies based at least in part on the duty cycle of the high side switch.
    Type: Application
    Filed: October 26, 2022
    Publication date: May 2, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventors: Michele Suraci, Giorgio Oddone, Paolo Selvo
  • Publication number: 20240146253
    Abstract: An amplifier circuits inductive/magnetic sensor interface can include a main signal path including one or more amplifiers configured to receive an input signal and to produce an output signal based on the input signal. The input signal may include a square-wave demodulated signal having an associated modulation frequency and an undesired frequency component at twice the modulation frequency of the square-wave demodulated signal. The amplifier circuit may include a gain feedback loop configured to set a gain of the amplifier circuit. The amplifier circuit may include a ripple reduction feedback loop configured to receive an intermediate signal on the main signal path and extract the undesired frequency component of the intermediate signal to produce a filtered version of the intermediate signal and provide the filtered version of the intermediate signal to the main signal path.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 2, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventors: Hernán D. Romero, Pablo Aguirre
  • Patent number: 11972154
    Abstract: Configurable variable-length shift register circuits include a group of flip-flops connected in a serial configuration. The plurality of flip-flops is connected to a serial data-in line and a clock line. Each flip-flop can include a data input, a clock input configured to receive a clock signal from the clock line, and a data output. The plurality of flip-flops can include a serial data-out line. The circuit includes a plurality of multiplexers connected to the plurality of flip-flops to enable a desired number of flip-flops for an application. A nonvolatile memory can be connected to the plurality of multiplexers and configured to receive a register-length indication, where the register-length indication corresponds to a selected number of flip-flops selected for enablement for a given application.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: April 30, 2024
    Assignee: Allegro MicroSystems, LLC
    Inventor: Matthew Hein
  • Patent number: 11973008
    Abstract: Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: April 30, 2024
    Assignee: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Shixi Louis Liu, William P. Taylor
  • Patent number: 11971463
    Abstract: Disclosed is a MTJ sensing circuit for measuring an external magnetic field and including a plurality of MTJ sensor elements connected in a bridge configuration, the MTJ sensing circuit having an input for inputting a bias voltage and generating an output voltage proportional to the external magnetic field multiplied by the bias voltage and a gain sensitivity of the MTJ sensing circuit, wherein the gain sensitivity and the output voltage vary with temperature; the MTJ sensing circuit further including a temperature compensation circuit configured to provide a modulated bias voltage that varies as a function of temperature over a temperature range, such that the output voltage is substantially constant as a function of temperature. Also disclosed is a method for compensating the output voltage for temperature.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: April 30, 2024
    Assignee: Allegro MicroSystems, LLC
    Inventors: Anuraag Mohan, Robert Zucker
  • Publication number: 20240133977
    Abstract: In one aspect, a method of manufacturing a magnetoresistance (MR) element having layers include ramping up a temperature of a reference layer of the MR element to an annealing temperature of the reference layer by increasing an amplitude of laser pulses applied to the reference layer over time to an amplitude that corresponds to the annealing temperature of the reference layer; applying a magnetic field to the reference layer; and maintaining the amplitude of subsequent laser pulses over time that have the amplitude that corresponds to the annealing temperature of the reference layer until at least the reference layer is annealed.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 25, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventors: Samridh Jaiswal, Paolo Campiglio, Sundar Chetlur
  • Patent number: 11967650
    Abstract: In one aspect, a diode includes a substrate having a first type dopant; a buried layer having a second type dopant and formed within the substrate; an epitaxial layer having the second type dopant and formed above the buried layer; and a plurality of regions having the first type dopant within the epitaxial layer. The plurality of regions includes a first region, a second region, and a third region. The diode also includes a base well having the first type dopant and located within the epitaxial layer and in contact with the third and fourth regions. In a reverse-bias mode, the diode is an electrostatic discharge (ESD) clamp and forms parasitic transistors comprising a first bipolar junction transistor (BJT), a second BJT and a third BJT.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: April 23, 2024
    Assignee: Allegro MicroSystems, LLC
    Inventors: Sagar Saxena, Washington Lamar, Maxim Klebanov, Chung C. Kuo, Sebastian Courtney, Sundar Chetlur
  • Patent number: 11961920
    Abstract: An integrated circuit package and method of fabrication are described. The integrated circuit package includes a lead frame having a first surface and a second opposing surface and a semiconductor die having a first, active surface in which circuitry is disposed and a second opposing surface attached to the first surface of the lead frame. A magnet attached to the second surface of the lead frame has a non-contiguous central region and at least one channel extending laterally from the central region. An overmold material forms an enclosure surrounding the magnet, semiconductor die, and a portion of the lead frame.
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: April 16, 2024
    Assignee: Allegro MicroSystems, LLC
    Inventors: Ravi Vig, William P. Taylor, Paul A. David, P. Karl Scheller, Andreas P. Friedrich
  • Publication number: 20240120371
    Abstract: Methods and apparatus for a device that includes a circuit, such as a memory cell, and an isolation structure to electrically isolate the circuit cell. The isolation structure can include a p-type substrate, a first series of p-type material extending to the p-type substrate, and a second series of p-type material extending to the p-type substrate. The first series of p-type material, the p-type substrate, and the second series of p-type material surrounds a first side, a second side, and a bottom of the circuit cell to electrically isolate the circuit cell with continuous p-type material. In some embodiments, the first series of p-type material comprises p-type well regions. In some embodiments, the first series of p-type material comprises deep trench isolation.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventors: James McClay, Maxim Klebanov, Sundar Chetlur, Thomas S. Chung
  • Patent number: 11953395
    Abstract: Differential magnetic field torque sensors include first and second magnetic field concentrators that guide magnetic flux to a magnetic field sensor from first and second magnetic field directors and a target, such as a multipole magnet assembly configured as a ring magnet. The magnetic field concentrators have pairs of sections that are interdigitated and configured adjacent to magnetic field sensing elements of the magnetic field sensor. The magnetic field directors can each have a plurality of teeth, which can be interdigitated and adjacent or proximate to the target. The magnetic field directors can be configured to be mounted as a unit to a rotatable shaft while the target can be configured to be mounted to a different rotatable shaft. The magnetic field concentrators and magnetic field sensor can be fixed while the magnetic field directors and target can rotate with respect to each other about a twist axis.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: April 9, 2024
    Assignee: Allegro MicroSystems, LLC
    Inventor: Alexander Latham
  • Patent number: 11953565
    Abstract: In one aspect, bridge circuitry includes a first magnetoresistance (MR) element connected with a second MR element at a first node; a third MR element connected with the first MR element at a second node; a fourth MR element connected with the third MR element at a third node; a fifth MR element connected with a sixth MR element at a fourth node; a seventh MR element connected with the fifth MR element at a fifth node; and an eighth MR element connected with the seventh MR element at a sixth node; and a plurality of eight switches. Six of the plurality of eight switches are each connected to a corresponding one node.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: April 9, 2024
    Assignee: Allegro MicroSystems, LLC
    Inventor: Hernán D. Romero
  • Publication number: 20240110777
    Abstract: Methods and apparatus receiving data at a first time from at least one sensor, determining a parameter from the received data for the first time, estimating the parameter for a future time based on the data for first time, and outputting the estimated parameter for the future time to a receiving device. In some embodiments, an IC package can process the received data to generate the estimated parameter for the future time. The IC package may transmit the estimated parameter using a particular protocol. In some embodiments, the receiving device can treat the estimated parameter as real-time data.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Applicant: Allegro MicroSystems, LLC
    Inventors: Emanuele Andrea Casu, Nicolás Rigoni, Ross Eisenbeis