Abstract: A method and apparatus of displaying video and graphics data together in a computer graphics display using only the memory needed for the graphics display includes determining the location of the video window in the frame buffer, writing video data to the portion of the frame buffer bounded by the video window. During the raster scan of the frame buffer, if the raster position is within the video window, video data are read from the video data addresses within the video window. When the displayed video window position is changed, the video data are moved accordingly.

Abstract: Integrated circuits having single and multiple device modes are described. In a preferred random access memory (RAM) embodiment, a first static RAM (SRAM) 10a having a "by n" input/output (I/O) configuration is fabricated adjacent to a second SRAM 10b having the same I/O configuration. An interconnect scheme 14 spans a single device scribe line 18 that separates SRAM 10a from SRAM 10b, and carries address, timing, and control signals between the adjacent SRAMs (10a and 10b). In the event single SRAMs of a ".times.n" configuration are desired, the wafer is sawed along the single device scribe line 18 severing the interconnect scheme 14. In the event multiple device SRAMs of a ".times.2n" configuration are desired, the wafer is sawed into multiple device dies, and the interconnect scheme kept intact.

Abstract: An improved laser fusible link structure for semiconductor devices (200) and method of manufacturing thereof (10) is disclosed. A first conductive layer is patterned to create a laser fuse (202) and then covered with a first dielectric layer (212). An etch mask layer, in the preferred embodiment a second layer of polysilicon, is deposited and patterned to form a fuse etch mask (214) directly over the laser fuse (202). The fuse etch mask (214) has a width that is smaller than a minimum laser spot size, but large enough to protect the laser fuse (202) from fuse window over-etch, taking into account any potential misalignment between the laser fuse (202) and the fuse etch mask (214).

Abstract: A random access memory (RAM) (10) is disclosed. A network of driver lines (28) extends over a number of core arrays (12a-12p) connecting a control bank 24 with column decode banks (26a and 26b), and the column decode banks (26a and 26b) with sense banks 46 within the core arrays (12a-12p). The driver lines 28 include predecode lines 30 and clock lines 32 for coupling predecode signals and clock signals from the control bank 24 to the column decode banks (26a and 26b). In addition, the driver lines 28 include column select lines 34 and sense driver lines 36 for coupling column select signals and sense amplifier enable signals from the column decode banks (26a and 26b) to the sense banks 46. The sense banks 46 include sense amplifiers 80 that are shared between array quadrants 42 by decoded transfer gate banks (70a and 70b). Advantageous placement of precharge circuits 82 and equalization circuits 86 provides a compact sense bank structure 46.

Abstract: A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-chip frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.

Abstract: A dynamic random access memory cell and method of fabrication thereof are disclosed. An access transistor (10) is formed in a substrate (12). The deposition of a first dielectric layer (20) follows. A plurality of conductive layers (22-30) are deposited, with alternating layers (24 and 28) having a higher dopant concentration than the other layers (22, 26 and 30). A contact hole (32) is etched through the conductive layers (22-30) and the first dielectric layer (20) to the substrate (12). A contact layer (36) is then deposited, making contact with the substrate (12) and each conductive layer (22-30). The conductive layers (22-30) and contact layer (36) are patterned with an isotropic etch selective to the higher doped layers (24 and 28). The resulting structure is a conductive member (42) with a peripheral side surface (44) having inset furrows (40) formed by the selective etching of the higher doped layers (24 and 28). A conformal capacitor dielectric (46) is formed over the conductive structure (42).

Abstract: A structure and method are provided for reducing DRAM cell area by eliminating the contact-to-gate spacing requirement while increasing the capacitor area by designing the capacitor to extend inside the contact, without sacrificing the sidewall capacitance. The new structure uses a self-aligned contact where the contact can overlap the gate region in the layout.

Abstract: A dynamic random access memory (DRAM) (10) is disclosed. Memory cell arrays (12) within the DRAM have word lines and bit lines, the bit lines being logically divided into bit line sections (26a-p). Corresponding to each bit line section (26a-p) is a sense/decode section (28a-p) having a fast and slow sense mode of operation. When data are read from a particular bit line section (26a-p) the corresponding sense decode section (28a-p) operates in the fast sense mode while the remaining sense/decode sections (28a-p) operate in the slow sense mode, providing for lower power consumption and/or faster access speeds.

Abstract: A display refresh system (10) is disclosed wherein a display image is stored in a screen memory (12) as a number of screen rows (26) having consecutive addressable units. A redundancy memory (38) includes a redundancy row (48) corresponding to each screen row (26). Each redundancy row (48) stores run length data that indicates the number of identical consecutive addressable units within a screen row (26). Addressable units are written with accompanying run lengths to a FIFO (54). A register repeater (56) repeats the addressable unit at the FIFO output (62) a number of times equal to the run length. The run length is used to advance the refresh address to the next group of identical consecutive addressable units within the screen row (26).

Abstract: An output buffer circuit with low power pre-output driving capability uses existing output drivers and includes input inverters with three-state outputs interposed between the input and output stages and a feedback circuit with three-state outputs connected to the output stage. During normal data transmission, the input inverters buffer the incoming complementary data signals driving the pull-up and pull-down transistors in the output stage while the three-state outputs of the feedback circuit are turned off. Upon receiving an active pre-output control signal, the input inverters are disabled, thereby isolating the pull-up and pull-down transistors from the incoming complementary data signals, and the feedback circuit is enabled. The enabled feedback circuit monitors the signal level of the output signal from the output stage.

Abstract: A display control circuit controls the outputs of the three video DACs of an RGB monitor on a window-to-window basis to enable the display of motion video and text on the same screen with different brightness and/or tint. A digital overdrive signal, synchronized to the video DAC digital inputs, is used to enable added DAC elements for the pixels in the video windows only. Stored digital instructions determine how many and which added DAC elements are enabled by the overdrive bit(s). By storing different instructions for each of the three video DACs, the circuit may also provide window-dependent tint control. By increasing the number of bits of digital data synchronized to the digital DAC inputs, the stored instructions may be reduced or eliminated. In this case, each of several windows may be set to differing brightness and tint levels.

Abstract: A word line driver circuit (10) for driving four word lines (18) is disclosed. In a preferred embodiment, the word line driver circuit (10) includes a decoder circuit (12) for pulling a decode node (20) to a logic low level (Vss) in response to internal row decode signals, a pull-up circuit (14) for pulling the decode node (20) to a logic high (Vcc) to deselect the word lines (18), four transfer transistors (NO) intermediate the decode node (20) and four control nodes (22), four CMOS inverters (18), each driving one word line (18) between a boost voltage and Vss. A PMOS level shifter transistor (P0) is associated with each inverter (18), and has a channel width that is small relative to both the channel widths of the transfer transistors (N0) and to the devices making up the decoder circuit (12), allowing the level shifter transistors (P0) to be overpowered by the decoder circuit (12).

Abstract: A burst dynamic random access memory (DRAM) (10) is disclosed having memory cells arranged in a number of quadrants (22), each quadrant including local I/O lines (24) for accessing the memory cells therein. The local I/O lines (24) of each quadrant are commonly coupled to global I/O lines (26) by tri-state driver banks (30). According to a row address and a first portion of a column address, a row decoding circuit (36) and column decoding circuit (40) couple one set of local I/O lines (24) within each quadrant (22) to selected columns within the quadrants (22). A bank sequencer (48) receives a second portion of the column address and generates burst sequence of different bank select signals. Each bank select signal enables a different set of tri-state driver banks (30). The enabled tri-state driver banks (30) provide a data path between the local I/O lines (24) and the global I/O lines.

Abstract: A switchable current source (10) for video DACs that reduces output transients. The switchable current source (10) includes a current mirror (20) connected to a cascode pair (22) for providing a reference current input and a current output. Connected to the reference current input is reference current generator (14) that includes p-channel transistor Q5 for providing a reference current according to the voltage applied at its gate by voltage source (24). A current switch (16) is connected to the current output and includes p-channel transistor Q6 for providing a path to ground and p-channel transistor Q7 for providing a path to an output node. In response to a decoder input DEC, an enable signal generator (18) outputs an enable signal EN and an inverted enable signal ENI to Q7 and Q6, respectively.

Abstract: A method and apparatus for dynamically regrouping display memory chips to efficiently implement 8-bit, 16-bit, and 24-bit per pixel display solutions is provided. The invention permits the implementation of 24-bit per pixel solutions in which 24-bit pixels do not straddle addressable regions, but without requiring the use of a unused byte of display memory per 24-bit pixel.

Abstract: A timing control circuit (10) is disclosed that provides a timing circuit (12) for controlling the operation of an I/O path circuit (14) in a synchronous static random access memory (SRAM). In a read or write operation, the timing circuit (12) sequentially disables bit line equalization circuits (34), enables sense amplifiers (38), disables I/O line equalization circuits (42), and enables secondary sense amplifiers (44). Further, the timing control (12) initiates a reset operation prior to the completion of the read or write operation. The reset operation includes sequentially enabling the bit line equalization circuits (34), disabling the sense amplifiers (38), enabling the I/O line equalization circuits (42), and disabling the secondary sense amplifiers (44). The timing circuit (12) includes first, second and third delay circuits (20, 22, and 24) to allow for minimum split times for bit line pairs (32) and I/O line pairs (40), and minimum secondary sense amplifier (44) sensing times.

Abstract: The use of nitrogen doped amorphous silicon as an electrode material for a semiconductor integrated circuit is described. A preferred embodiment is a single transistor flash EPROM cell is disclosed having a tunnel dielectric (202), a floating gate (206), an intergate dielectric having three layers (208, 210, 212), and a control gate (218). The floating gate (206) is composed of in-situ nitrogen doped amorphous silicon. Due to the nitrogen doping the floating gate (206) retains its microcrystalline structure under high temperatures, eliminating large grain boundaries in the floating gate (206). As a result, arrays composed of the disclosed EPROM cell have improved memory cell threshold (V.sub.TM) distributions. In addition, silicon oxide grown from the the floating gate (206) has fewer stress induced defects reducing leakage paths that contribute to data retention errors.An alternate embodiment uses nitrogen doped amorphous silicon as the capacitor plates (304 and 306) in a DRAM cell (300).

Abstract: A timing delay modulation scheme for integrated circuits (10) is disclosed. A super voltage is applied to existing bond pads (30) and detected by super voltage detect circuits (34) which generate a number of logic input signals (22) to a logic unit (18). In response, the logic unit (18) provides a number of control signals (24) which are coupled to timing adjust circuits (20). In the preferred embodiment, in response to its respective control signals, each timing adjust circuit (20) pushes-out or pulls-in, a separate internal timing signal (S0-S3) of the integrated circuit. The super voltage detect circuit (34) includes an adjustable effective super voltage level, and is capable of being disabled. Further, the timing adjustment provided by each timing adjust circuit (20) can be altered.

Abstract: A synchronous burst SRAM (110) is disclosed that includes a clock circuit (112) having a phase correction subcircuit (134) and a clock routing subcircuit (132). The clock routing subcircuit (132) provides an internal clock signal to at least one clocked circuit. The phase correction subcircuit (134) is a modified phase locked loop that includes a phase comparator (138) that receives an external clock signal and a delayed internal clock signal. In response to the signals, the phase comparator (138) provides a phase error signal to a charge pump (140) which is coupled to a loop filter (142) to provide an error voltage. The error voltage is coupled to a VCO (144) which provides the internal clock signal as an output. The internal clock signal is coupled to the input of the phase comparator (138) by a feedback circuit which generates the delayed internal clock signal for the phase comparator (138).

Abstract: A burst mode static random access memory (SRAM) (10) is disclosed that includes an address transition detect signal (ATD) generating circuit (14) that provides either an asynchronous ATD signal (a-ATD) or a synchronous ATD signal (s-ATD) depending upon the logic state of a mode signal (ATM). A rising edge of the a-ATD signal is generated by a change in address. A falling edge is generated after a predetermined time period according an a-ATD circuit (60) within the ATD generating circuit (14). A falling edge of the s-ATD signal is generated by a rising edge of an internal synchronous clock pulse (CLAT). The rising edge of the s-ATD signal is generated when data are sensed on data lines (40) by an end-of-cycle circuit (20). If ATM is high, the a-ATD signal is used for timing on the SRAM (10). If ATM is low, timing is determined according to the s-ATD signal. An ATD control circuit (16) is provided to generate I/O control signals in response to the ATD signal (either s-ATD or a-ATD).