Abstract: A delay-locked-loop (DLL) that has increased precision and a wide range of operation is formed by utilizing a chain of delay blocks to add or subtract a discreet amount of delay, and a voltage-controlled delay line (VCDL) to add or subtract a smaller amount of delay. The delay blocks allow the delayed clock signal to get close to the reference clock signal, while the VCDL allows the delayed clock signal to lock onto the reference clock signal.

Abstract: A low latency method of synchronizing asynchronous data to a core clock in a receiving device. A communication referenced to a transmitting clock that is asynchronous to the core clock is received at a receiving device. The communication includes a synchronization signal which is propagated through a synchronizer in the receiving device to synchronize the signal to the core clock. Upon receipt of the synchronization signal by the synchronizer, a load pointer for loading received data into a buffer synchronous with the transmitting clock is reset. Upon completion of the propagation of the synchronization signal through the synchronizer, an unload pointer for unloaded the data from the buffer synchronous with the core clock is reset. The unload pointer is then offset by an amount that compensates for the delay incurred while the synchronization propagated through the synchronizer.

Abstract: The present invention provides a unique system and method for optimizing packet processing flow in a communications network by minimizing latency associated with packet-forwarding eligibility determinations. The present invention employs a speculative scheme with automatic recovery, including a two-way multithreaded implementation designed to overcome the aforementioned latency issue, including the functionality of enqueuing an incoming packet in both packet memory and a cut through buffer; determining the packet's eligibility for cutting through the buffer; and based on the determination, rolling back the unsuccessful process.

Abstract: The dynamic random access memory (DRAM) cells in a semiconductor chip are isolated from the peripheral circuitry by forming the DRAM cells directly in the substrate while the peripheral and other functional circuits are formed in wells that are isolated from the substrate. In addition to providing isolation, the placement of the DRAM cells also reduces the leakage current in the cells, thereby increasing the time that a DRAM cell can hold a charge without being refreshed.

Abstract: The diode drops associated with the output voltage from a conventional charge pump are eliminated in the present invention with a dual-chain charge pump that utilizes the pumped voltages from each charge pump chain to drive the gates of the other charge pump chain. As a result, the voltages on the gates of the transistors are pumped up to a level such that there is no threshold voltage drop across the transistor, and thus, making it behave like an ideal switch.

Abstract: A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures.

Abstract: A flash EPROM cell (10) is disclosed having increased capacitive coupling between a floating gate (28) and a control gate (32). Vertical structural elements (34a and 34b) are formed on field oxide regions (20) on opposing sides of the flash EPROM cell channel 20, in the channel width direction. The structural elements (34a and 34b) include relatively vertical faces. The floating gate (28) conformally cover the channel 20 and the vertical faces of the structural elements (34a and 34b). The control gate (32) conformally covers the floating gate (28). The vertical displacement introduced by the structural elements (34a and 34b) increases the overlap area between the floating gate (28) and the control gate (32) without increasing the overlap area of the floating gate (28) and the channel 20, resulting in increased capacitive coupling between the control gate (32) and the floating gate (28).

Abstract: A method of manufacturing integrated circuits having single and multiple device modes is described. In a preferred random access memory (RAM) embodiment, a first static RAM (SRAM) 10a having a “by n” input/output (I/O) configuration is fabricated adjacent to a second SRAM 10b having the same I/O configuration. An interconnect scheme 14 spans a single device scribe line 18 that separates SRAM 10a from SRAM 10b, and carries address, timing, and control signals between the adjacent SRAMs (10a and 10b). In the event single SRAMs of a “×n” configuration are desired, the wafer is sawed along the single device scribe line 18 severing the interconnect scheme 14. In the event multiple device SRAMs of a “×2n” configuration are desired, the wafer is sawed into multiple device dies, and the interconnect scheme kept intact.

Abstract: A flash EPROM array (100) and method of manufacture is disclosed. Source regions (118a-118f) are shared between the memory cells (108a,l-108d,n) of row (104a-104d) pairs, and are isolated from one another in the row direction by isolation regions 120. Low resistance source conductor members (122a-122b) extend in the row direction and are formed over the source regions (118a-118f) and make contact therewith in a self-aligned fashion. The architecture allows for source decoding and thus enables user programmable sector erase architecture.

Abstract: A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures.

Abstract: A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures.

Abstract: A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-chip frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.

Abstract: A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-chip frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.

Abstract: A switch/router circuit integrates a multi-port memory array with the Media Access Control (MAC) units to facilitate direct transfer of packet payloads to the destination port. The store and forward functions are performed using a single memory cell with multiple pass gates, one pass gate designated for each MAC port. That is, a switch router is implemented using the multi-port memory array such that the number of ports in each memory cell is proportional to the number of MACs integrated in the single monolithic chip. An arbitrator arbitrates between the integrated ports, a lookup table identifies the destination port and a system controller controls all of the integrated elements.

Abstract: In one aspect, the current invention provides a method for reducing the source leakage of a semiconductor device. The method comprises the steps of stacked gate etch, thin oxide formation, SAS etch, spacer formation and source implant on the semiconductor substrate. In a second aspect, the current invention provides another method for reducing the source leakage of a semiconductor device. The method comprises the steps of stacked gate etch, first oxide layer formation, first source implant, annealing, SAS etch, second oxide layer formation, spacer formation, and second source implant. In yet another aspect, the current invention provides a novel semiconductor device. The semiconductor device is comprised of a stacked gate provided on a portion of a semiconductor substrate, a first oxide layer appended to the stacked gate, a second oxide layer formed on the first oxide layer and a spacer formed on the second oxide layer.

Abstract: The present invention provides a monolithic or discrete high speed/low speed interface that is capable of interfacing with the high speed subsystems of a data processing system and low speed subsystems of a data processing system. In one embodiment, the high speed/low speed interface subsystem of the present invention comprises a high speed interface for interfacing with high speed subsystems via a high speed bus, a low speed interface for interfacing with low speed subsystems via a low speed bus, a control circuitry coupled to both the high speed and low speed interfaces, and an internal bus coupled to the control circuitry and the high speed and low speed interfaces. The control circuitry controls the transfer of information between the interfaces. In a second embodiment of the present invention, the high speed/low speed interface subsystem of the present invention comprises all the elements of the first embodiment and a prediction unit.

Abstract: According to the first embodiment of the present invention, a pre-charge device is connected to the middle of each complementary bit line. Thus, once activated, the pre-charge device only drives a load equal to half of the RC impedance of the entire bit lines during the pre-charging operation. According to the second embodiment of the present invention, a first pre-charge device is connected to one end of each complementary bit lines and a second pre-charge device is connected approximately to the middle of each complementary bit lines. Once both devices are activated, each device drives a load equal to half of the RC impedance of the entire bit lines, thus reducing the pre-charge time of the bit lines.

Abstract: A flash EPROM cell (10) is disclosed having increased capacitive coupling between a floating gate (28) and a control gate (32). Vertical structural elements (34a and 34b) are formed on field oxide regions (20) on opposing sides of the flash EPROM cell channel 20, in the channel width direction. The structural elements (34a and 34b) include relatively vertical faces. The floating gate (28) conformally cover the channel 20 and the vertical faces of the structural elements (34a and 34b). The control gate (32) conformally covers the floating gate (28). The vertical displacement introduced by the structural elements (34a and 34b) increases the overlap area between the floating gate (28) and the control gate (32) without increasing the overlap area of the floating gate (28) and the channel 20, resulting in increased capacitive coupling between the control gate (32) and the floating gate (28).

Abstract: Provided is a method of forming self-aligned contacts in salicided MOS devices that provides improved reliability and decreased resistance relative to conventional tungsten polycide processing. Self-aligned contacts in salicided MOS devices are also provided. The method makes use of a metal, preferably titanium or cobalt, which is deposited on the devices' gates and diffusion regions and converted to a silicide with a resistance substantially less than that of tungsten silicide, preferably by RTA processing. A self-aligned contact etch stop mask is then formed over the gates and a portion of sidewall spacers on the gates. The presence of this “oversize” self-aligned contact etch stop mask prevents shorting of the subsequently deposited contact interconnect material to the gates, while allowing silicidation of the diffusion regions as well as the gates with a low resistance silicide, thereby improving device reliability and decreasing resistance.

Abstract: A flash EPROM device (100) is disclosed. During a programming operation, a primary programming voltage circuit (116) drives I/O lines (110) to a programming voltage (Vp) according to input data values. Secondary programming voltage circuits (118) are located remotely from the primary programming voltage circuit (116) and further drive I/O lines to Vp in response to the voltage levels on the I/O lines. This arrangement reduces the effect on the load line response of the impedance intermediate the primary programming voltage circuit (116) and the secondary programming voltage circuits (118).