Abstract: A clamping circuit for clamping a circuit node during an initial circuit powerup interval includes a switching circuit and a switching control circuit. The switching circuit is an N-MOSFET with its drain and source terminals connected to circuit ground and the subject node sought to be clamped, respectively, and its gate terminal connected to the switching control circuit. The switching control circuit includes a number of N-MOSFETs which are interconnected in such a manner as to receive the power supply voltage and generate a switching signal which turns the switching circuit N-MOSFET on during an initial circuit powerup interval to clamp the subject node and then off after the power supply has reached a preselected minimum value. Upon initial circuit powerup, the switching control circuit self-triggers itself to turn the switching circuit on and clamp the subject node at ground potential.

Abstract: A dual-port semiconductor memory device is disclosed that includes a number of array blocks (12) having memory cells disposed in rows and local columns, with each local column having a local bit line pair (30). A sense amplifier row (28) is associated with each array block (12) and includes a sense amplifier (28) coupled to each local bit line pair (30). Each sense amplifier row (14) is commonly connected through a number of bit line gates (32) to global bit line pairs (26) disposed on a higher fabrication layer than that of the local bit lines (30). A block decode signal commonly activates all the bit line gates (32) of one array block to couple the global bit lines (26) to one sense amplifier row (14). The global bit lines (26) are also connected to a column decoding section (18) which provides random input/output selection of a global bit line pair (26). A latch row (20) is also coupled to the global bit lines ( 26) through a number of latch gates (42).

Abstract: A semiconductor random access memory (RAM) is disclosed having a number of array blocks (14), each array block (14) including standard rows, standard columns, redundant rows (24) and redundant columns (26). A row redundancy circuit (44) is provided for each array block that includes a single row fuse bank (28). Within the row fuse bank (28) are row disable fuses (42) and redundant row fuses (54) interspersed at regular intervals between the row disable fuses (42). Each row disable fuse (42) disables a standard row segment (32) when opened. A redundant row segment (46) is driven according to the combination of opened redundant row fuses (54). A column redundancy circuit (62) includes a number of column fuses (64) disposed in a column fuse bank (30). Redundant columns (26) are enabled by opening selected ones of the column fuses (64). If a redundant column (26) is driven the remaining standard columns of its associated array block (14) are disabled.

Abstract: A pre-sense amplifier (10) is disclosed. The pre-sense amplifier (10) increases a low-going bit line signal from a cell column (24) by an amount approximately equal to the threshold voltage of an n-channel MOS transistor. The pre-sense amplifier (10) includes a first channel (12) and a second channel (14), each channel having a precharge/transfer transistor (16) and an output precharge transistor (18). The output precharge transistors (18) are clocked to pull the inputs to a sense amplifier (26) to a positive supply voltage. At the same time, the precharge/transfer transistors (16) precharge the bit lines of a cell column (24) to a voltage equal to the positive supply voltage less their threshold voltage. When the cell column (24) pulls one of the bit lines low, the corresponding precharge/transfer transistor (16) connects the bit line with the sense amplifier input, redistributing the charge across the bit line capacitance and the sense amplifier input capacitance.

Abstract: An improved redundancy scheme for monolithic memory devices is disclosed. A memory device (10) has a quadrant array (12) of main memory quadrants (14). Each main memory quadrant (14) includes a number of memory cells arranged in a number of main memory rows (26) and main memory columns (28). A first level of redundancy is provided within each main memory quadrants (14) which has local redundant rows (36) and local redundant columns (38) for replacing defective cells therein. A second level redundancy is provided by redundant memory sections (20) which are used in combination to replace main memory quadrants (14) if necessary. The redundant memory sections (20) are disposed along the edge of the quadrant array (12). A third level of redundancy is provided by redundant section rows (52) and redundant section columns (54) within each redundant memory section (20) to replace defective cells therein.

Abstract: A method of manufacturing a flash EPROM cell is disclosed. A flash EPROM gate stack (114) is formed on p-type silicon substrate (100) having tunnel oxide (102) thereon. The gate stack (114) includes a polysilicon floating gate (106), an intergate dielectric (108), and a control gate (116). The substrate (100) includes a source region (120), a channel (122) and a drain region (118) therebetween. A source implant mask (124) is created that covers at least the drain region (118) and leaves the source region (120) exposed. Large angle ion implantation is used to implant a source dopant into the source region (120) below the floating gate (106) of the gate stack (114). The source implant mask (124) is stripped and the source and drain regions (118 and 120) are doped with a source/drain implant by ion implantation at an implant angle of approximately zero degrees (.about.0.degree.).

Abstract: A self-timed synchronous clock pulse circuit (100) is disclosed that includes a pulse pull-down circuit (102) pulling a first pulse node (104) to ground upon receiving the rising edge of an external clock. A pulse generator (108) responsive to a high-to-low transition at the first pulse node (104) generates a second clock pulse. A pulse pull-up circuit (110) is responsive to the second edge of the second clock pulse and pulls the first pulse node (104) to the positive power supply. An initialization circuit (112) is provided to prevent a lock-up condition upon power-up by sampling the logic level of the first pulse node (104) on the rising edge of the external clock. The logic value is essentially held throughout the remainder of the clock cycle by gating the value into a second latch during the second portion of an external clock cycle.

Abstract: A row driving circuit (10) having a reduced number of transistors provides range of row deselect voltages, and eliminates the need for an NMOS pull-down device. The row driving circuit (10) has a-level shifter (14) formed by a PMOS input pull transistor P1 that is drain coupled at node V 10 to an NMOS input transistor N1. N1 functions as passgate for a row select signal and inverted row select signal applied to its gate and source respectively. A PMOS row pull-up transistor P2 has its gate coupled to V 10, its source coupled to a variable positive supply voltage (12), and its drain coupled to the source of a PMOS row select transistor P3. The drain and gate of P3 are coupled to switching circuits S 11 and S 12 respectively. S 11 and S 12 provide gate and drain voltages to quickly deselect the row by pulling the row to a negative deselect voltage. A PMOS erase transistor is also source coupled to the row with its gate coupled to switching circuit S 13 and its drain coupled to switching circuit S14.

Abstract: An address transition detection (ATD) circuit provides an address transition detection pulse in response to either a high-to-low or low-to-high external address transition. The ATD circuit includes an address buffer that translates an externally applied address signal into an internal address signal and its logical complement. Two delay chains, each of which includes inverters, capacitors, a NAND gate and a CMOS pass gate, combine with the address buffer and an n-channel pull-down transistor to provide the ATD circuit. The outputs of the CMOS pass-gates are connected to the gate of the pull-down transistor. The drain of the pull-down transistor serves as the local ATD node of a dual-load feed-back controlled ATD pulse generator. The ATD local node is common to address buffers that select memory cells within a particular memory block. Address buffers responsible for switching between blocks have separate feedback-controlled ATD pulse generators in order to optimize the access time of the memory device.

Abstract: A design approach for a tree structure multiplexer produces a compact circuit layout by reducing the required number of transistors. The multiplexer is used to perform a binary decode of the input signals to generate a single selection of one of a number of potential outputs. since the inputs undergo a binary decode, the number of outputs is equal to 2.sup.x, where x is the number of inputs.

Abstract: A flash EPROM memory cell array includes a plurality of flash cells arranged as a matrix of rows in columns of said cells. Each cell includes a single transistor. For each row of flash cells in the matrix, a corresponding bit line is connected to the drain region of each memory cell transistor in that row. For each column of flash cells, a corresponding wordline is connected to the control gate of each memory cell transistor in that column. Bias circuitry is provided for applying read bias voltages to the array for reading data from a selected cell in the matrix. The read bias circuitry includes means for applying a first control gate voltage to the wordline connected to the control gate of the selected cell and the second control gate voltage to the deselected wordlines.

Abstract: Hierarchical redundancy is implemented in a monolithic memory by providing standard row and column redundancy augmented by redundant blocks, each having its own internal row and block redundancy. The efficiency of the redundant blocks is further enhanced by subdividing the redundant blocks into individually replaceable segments of rows or columns. A test and repair algorithm utilizing the hierarchical redundancy scheme is also provided.

Abstract: An address detection transition circuit provides an address transition detection pulse in response to either a high-to-low or a low-to-high external address input logic transition. The address transition detection circuit includes an address input buffer that responds to the external address input by providing first and second complimentary signals at first and second address input buffer output nodes, respectively. A first delay chain connected between the first address input buffer output node and the buffer output node responds to a high-to-low external address input logic transition by providing a logic high signal at the buffer output node. Similarly, a second delay chain connected between the second address input buffer output node and the buffer output node responds to a low-to-high external address input logic transition by providing a logic high signal at the buffer output node.

Abstract: Methods and apparatus are provided for using a partially functional memory device with extra fail bits to create a fully functional monolithic device. The concept may be expanded for use in waferscale integration. The concept may also be used to create a fully functional memory board using partially functional memory chips. To accomplish this, a distinct fail bit array is added to each memory chip and the defective bits in the main chip are replaced by bits in the fail bit array using a programmable element, such as a programmable logic array (PLA). The PLA generates fail bit access addresses to locations in the fail bit memory that replace the defective bits in the main array. Thus, the external address is simultaneously applied to both the main array and to the PLA. If there is a match between the external address and an internal location in the PLA, the PLA outputs a flag and a fail bit address which are used to disable the main array access and to enable access to the fail bit memory.