Patents Assigned to Alpha and Omega Semiconductor, Inc.
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Publication number: 20130119394Abstract: A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.Type: ApplicationFiled: November 11, 2011Publication date: May 16, 2013Applicant: ALPHA AND OMEGA SEMICONDUCTOR INC.Inventors: TingGang Zhu, Anup Bhalla, Madhur Bodbe
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Patent number: 8436429Abstract: A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.Type: GrantFiled: May 29, 2011Date of Patent: May 7, 2013Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Yan Xun Xue, Yueh-Se Ho, Lei Shi, Jun Lu, Liang Zhao
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Patent number: 8431993Abstract: A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semiconductor die. Add a base registration feature onto base leadframe and a plate registration feature onto interconnection plate with the registration features designed to match each other such that, upon approach of the interconnection plate to base leadframe, the two registration features would engage and guide each other causing concomitant self-aligned attachment of the interconnection plate to base leadframe. Next, the interconnection plate is brought into close approach to base leadframe to engage and lock plate registration feature to base registration feature hence completing attachment of the interconnection plate to semiconductor die and forming a leadframe package.Type: GrantFiled: November 4, 2011Date of Patent: April 30, 2013Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Yan Xun Xue, Jun Lu, Lei Shi, Liang Zhao
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Patent number: 8426960Abstract: A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.Type: GrantFiled: December 21, 2007Date of Patent: April 23, 2013Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Ming Sun, Tao Feng, François Hébert, Yueh-Se Ho
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Publication number: 20130075808Abstract: A Schottky diode includes a semiconductor layer formed on a semiconductor substrate; first and second trenches formed in the semiconductor layer where the first and second trenches are lined with a thin dielectric layer and being filled partially with a trench conductor layer and remaining portions of the first and second trenches are filled with a first dielectric layer; and a Schottky metal layer formed on a top surface of the semiconductor layer between the first trench and the second trench. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in each of the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate.Type: ApplicationFiled: September 22, 2011Publication date: March 28, 2013Applicant: ALPHA AND OMEGA SEMICONDUCTOR INC.Inventors: Daniel Calafut, Yi Su, Jongoh Kim, Hong Chang, Hamza Yilmaz, Daniel S. Ng
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Publication number: 20130075746Abstract: A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: ALPHA AND OMEGA SEMICONDUCTOR INC.Inventors: Shekar Mallikarjunaswamy, François Hébert
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Publication number: 20130075741Abstract: A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: ALPHA AND OMEGA SEMICONDUCTOR INC.Inventors: Shekar Mallikarjunaswamy, François Hébert
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Patent number: 8399925Abstract: A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.Type: GrantFiled: February 12, 2010Date of Patent: March 19, 2013Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Xiaobin Wang, Anup Bhalla, Hamza Yilmaz, Daniel Ng
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Patent number: 8372738Abstract: This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein.Type: GrantFiled: October 30, 2009Date of Patent: February 12, 2013Assignee: Alpha & Omega Semiconductor, Inc.Inventor: Tinggang Zhu
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Patent number: 8367501Abstract: An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.Type: GrantFiled: March 24, 2010Date of Patent: February 5, 2013Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Sik Lui, Anup Bhalla
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Patent number: 8362606Abstract: A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.Type: GrantFiled: July 29, 2010Date of Patent: January 29, 2013Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Yueh-Se Ho, Yan Xun Xue
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Patent number: 8362585Abstract: A semiconductor junction barrier Schottky (JBS-SKY) diode with enforced upper contact structure (EUCS) is disclosed. Referencing an X-Y-Z coordinate, the JBS-SKY diode has semiconductor substrate (SCST) parallel to X-Y plane. Active device zone (ACDZ) atop SCST and having a JBS-SKY diode with Z-direction current flow. Peripheral guarding zone (PRGZ) atop SCST and surrounding the ACDZ. The ACDZ has active lower semiconductor structure (ALSS) and enforced active upper contact structure (EUCS) atop ALSS. The EUC has top contact metal (TPCM) extending downwards and in electrical conduction with bottom of EUCS; and embedded bottom supporting structure (EBSS) inside TPCM and made of a hard material, the EBSS extending downwards till bottom of the EUCS. Upon encountering bonding force onto TPCM during packaging of the JBS-SKY diode, the EBSS enforces the EUCS against an otherwise potential micro cracking of the TPCM degrading the leakage current of the JBS-SKY diode.Type: GrantFiled: July 15, 2011Date of Patent: January 29, 2013Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Anup Bhalla, Ji Pan, Daniel Ng
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Publication number: 20130015494Abstract: A termination structure for a semiconductor device includes an array of termination cells formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In other embodiments, semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches.Type: ApplicationFiled: September 21, 2012Publication date: January 17, 2013Applicant: ALPHA & OMEGA SEMICONDUCTOR, INC.Inventor: ALPHA & OMEGA SEMICONDUCTOR, INC.
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Patent number: 8354334Abstract: A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.Type: GrantFiled: October 21, 2011Date of Patent: January 15, 2013Assignee: Alpha & Omega Semiconductor Inc.Inventor: Il Kwan Lee
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Patent number: 8354740Abstract: A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate.Type: GrantFiled: December 1, 2008Date of Patent: January 15, 2013Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Kai Liu, François Hébert, Lei Shi
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Patent number: 8344499Abstract: A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.Type: GrantFiled: March 16, 2012Date of Patent: January 1, 2013Assignee: Alpha & Omega Semiconductor, IncInventors: Yuping Gong, Yan Xun Xue
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Publication number: 20120329238Abstract: A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS.Type: ApplicationFiled: September 6, 2012Publication date: December 27, 2012Applicant: ALPHA & OMEGA SEMICONDUCTOR, INC.Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla
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Patent number: 8338232Abstract: Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected.Type: GrantFiled: March 10, 2011Date of Patent: December 25, 2012Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Lei Shi, Yan Xun Xue, Yuping Gong
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Patent number: 8324053Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.Type: GrantFiled: September 30, 2009Date of Patent: December 4, 2012Assignee: Alpha and Omega Semiconductor, Inc.Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla
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Publication number: 20120299569Abstract: A control circuit for a switching regulator implements constant on-time control scheme with synchronous rectification and applies an integrated standard and light load control loop to improve light load efficiency and enhance transient response. In one embodiment, the control circuit includes a reference voltage selection circuit configured to select, based on a low-side current signal, a first reference voltage for standard load condition and a second reference voltage for light load condition as a selected reference voltage. The second reference voltage is greater than the first reference voltage. The control circuit further includes a control loop configured to generate a control signal to turn on the main switch when the feedback voltage is below the selected reference voltage and the minimum off-time duration has expired.Type: ApplicationFiled: March 21, 2012Publication date: November 29, 2012Applicant: ALPHA AND OMEGA SEMICONDUCTOR INC.Inventor: Zhiye Zhang