Abstract: A gallium nitride based semiconductor diode includes a substrate, a semiconductor body including a first heavily doped GaN layer and a second lightly doped GaN layer. The semiconductor body includes mesas projecting upwardly from a lower surface where each of the mesas includes the second GaN layer and a portion of the first GaN layer. Schottky contacts are formed on the upper surface of the mesas and ohmic contacts are formed on the lower surface of the semiconductor body. An insulating layer is formed over the Schottky and ohmic contacts and vias are formed in the insulating layer to the Schottky and Ohmic contacts. An anode electrode is formed in a first metal pad in electrical contact with the Schottky contacts. A cathode electrode is formed in a second metal pad in electrical contact with the ohmic contacts.

Abstract: A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes an auxiliary inductor in series with the main switching FET for inducing an auxiliary inductive voltage proportional to di/dt; an auxiliary FET in parallel with the main switching FET; the auxiliary FET gate is connected to produce a gate voltage equal to the auxiliary inductive voltage. When the di/dt tends to exceed a predetermined maximum rate of decrease the auxiliary FET produces an auxiliary current component counteracting further decrease of the di/dt. The main switching FET and the auxiliary FET can be formed from a single die with shared source and drain; the auxiliary inductor can be implemented as a parasitic inductance of an inherently required bonding wire connecting the main switching FET to its device terminal to simplify packaging with reduced cost.

Abstract: A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

Abstract: A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.

Abstract: A high-voltage field-effect device contains an extended drain or “drift” region including an embedded stack of JFET regions separated by intervening layers of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and the floor and ceiling of each JFET region is lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the JFET regions and in the drift region that separates the JFET regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the JFET regions from diffusing into the drift region.

Abstract: This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

Abstract: A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

Abstract: A semiconductor package is disclosed for packaging two adjacent semiconductor dies atop a circuit substrate. The dies are separated from each other along their longitudinal edges with an inter-die distance. An elevation-adaptive electrical connection connects a top metalized contact of die two to the bottom surface of die one while accommodating for elevation difference between the surfaces. The elevation-adaptive electrical connection includes: a) An L-shaped circuit route that is part of the circuit substrate, extending transversely from a die one longitudinal edge and placing an intermediate contact area next to a die two transverse edge. b) An interconnection plate connecting the top metalized contact area of die two with the intermediate contact area while being formed to accommodate for elevation difference between the contact areas. Consequently, the semiconductor package reduces the inter-die distance from an otherwise direct transverse circuit routing between the longitudinal edges of the dies.

Abstract: A hysteretic comparator is proposed for comparing input signals and producing an output signal VOT with a hysteresis window Vhys. The hysteretic comparator includes a differential input stage with current output (DICO) having input transistors with transconductance Gmtnx for converting the input signals, with an input stage transconductance Gmin, into intermediate signal currents. A steerable offset current generator, driven by a steering control signal, steers an offset current source IOS to alternative offset currents. A current-to-voltage summing converter (IVSC) sums up the intermediate signal currents and the offset currents and converts the result into VOT plus the steering control signal causing Vhys=IOS/Gmin. A feedback resistance RNF is connected to the input transistors to form a negative feedback loop. The RNF is sized such that GMin, hence Vhys, becomes essentially solely dependent upon the feedback conductance GNF=1/RNF independent of the Gmtnx thus its process and environmental variation.

Abstract: A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.

Abstract: A circuit is proposed for limiting maximum switching FET drain-source voltage (VDS) of a transformer-coupled push pull power converter with maximum DC supply voltage VIN—MAX. Maximum VDS is accentuated by leakage inductances of the push pull transformer and the power converter circuit traces. The limiting circuit bridges the drains of the switching FETs and it includes two serially connected opposing Zener diodes each having a Zener voltage Vzx. The invention is applicable to both N-channel and P-channel FETs. In a specific embodiment, Vzx is selected to be slightly ?2*VIN—MAX with the maximum VDS clamped to about VIN—MAX+½ Vzx. In another embodiment, a proposed power switching device with integrated VDS-clamping includes: a) A switching FET. b) A Zener diode having a first terminal and a second terminal, the second terminal of the Zener diode is connected to the drain terminal of the switching FET.

Abstract: This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.

Abstract: A method is disclosed for making a substantially charge balanced multi-nano shell drift region (MNSDR) for superjunction semiconductor devices atop a base substrate. The MNSDR has numerous concentric nano shell members NSM1, NSM2, . . . , NSMM (M>1) of alternating, substantially charge balanced first conductivity type and second conductivity type and with height NSHT. First, a bulk drift layer (BDL) is formed atop the base substrate. A substantially vertical cavity of pre-determined shape and size and with depth NSHT is then created into the top surface of BDL. The shell members NSM1, NSM2, . . . , NSMM are successively formed inside the vertical cavity, initially upon its vertical walls then moving toward its center, so as to successively fill the vertical cavity till a residual space remains therein. A semi-insulating or insulating fill-up nano plate is then formed inside the residual space to fill it up.

Abstract: A semiconductor device includes a first semiconductor layer and a second semiconductor layer of opposite conductivity type, a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches, and a second epitaxial layer of the second conductivity type formed on the first epitaxial layer where the second epitaxial layer is electrically connected to the second semiconductor layer. The first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, each having uniform doping concentration. The second epitaxial layer has a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration where the first and second thicknesses and the first doping concentration and second average doping concentrations are selected to achieve charge balance in operation.

Abstract: A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

Abstract: A gallium nitride based semiconductor diode includes a substrate, a GaN layer formed on the substrate, an AlGaN layer formed on the GaN layer where the GaN layer and the AlGaN layer forms a cathode region of the diode, a metal layer formed on the AlGaN layer forming a Schottky junction therewith where the metal layer forms an anode electrode of the diode, and a high barrier region formed in the top surface of the AlGaN layer and positioned under an edge of the metal layer. The high barrier region has a higher bandgap energy than the AlGaN layer or being more resistive than the AlGaN layer.

Abstract: A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS.

Abstract: A DC-DC buck converter in multi-die package is proposed having an output inductor, a low-side Schottky diode and a high-side vertical MOSFET controlled by a power regulating controller (PRC). The multi-die package includes a first die pad with the Schottky diode placed there on side by side with the vertical MOSFET. The PRC die is attached atop the first die pad via an insulating die bond. Alternatively, the first die pad is grounded. The vertical MOSFET is a top drain N-channel FET, the substrate of Schottky diode die is its anode. The Schottky diode and the vertical MOSFET are stacked atop the first die pad. The PRC is attached atop the first die pad via a conductive die bond. The Schottky diode die can be supplied in a flip-chip configuration with cathode being its substrate. Alternatively, the Schottky diode is supplied with anode being its substrate without the flip-chip configuration.

Abstract: The present invention discloses a power MOSFET device with an added tungsten spacer in its contact hole, and manufacturing methods for the device. The features of the device are as follows: It includes trench gate isolated in trench and source/body contacts formed in the contact hole, and the tungsten spacer between Ti/TiN barrier layer and aluminum metal layer, the tungsten spacer is deposited on the bottom corners of the contact hole to cover its bottom corners. The addition of tungsten spacer to the bottom corners of the contact hole can effectively eliminate the presence of pits at the corners and junction spiking due to poor step-coverage of the Ti/TiN barrier layer otherwise leading to direct contact of silicon with aluminum. Thus, the present invention prevents a power MOSFET device from failures due to Idss leakage thus insuring high device quality and yield.

Abstract: A gallium nitride based semiconductor diode includes a substrate, a semiconductor body including a first heavily doped GaN layer and a second lightly doped GaN layer. The semiconductor body includes mesas projecting upwardly from a lower surface where each of the mesas includes the second GaN layer and a portion of the first GaN layer. Schottky contacts are formed on the upper surface of the mesas and ohmic contacts are formed on the lower surface of the semiconductor body. An insulating layer is formed over the Schottky and ohmic contacts and vias are formed in the insulating layer to the Schottky and Ohmic contacts. A first metal pad is formed in a third metal layer and over vias to the Schottky contacts to form an anode electrode. A second metal pad is formed in the third metal layer and over vias to the ohmic contacts to form a cathode electrode.