Patents Assigned to Alpha and Omega Semiconductor, Inc.
-
Publication number: 20120282762Abstract: A method for forming a gallium nitride based semiconductor diode includes forming Schottky contacts on the upper surface of mesas formed in a semiconductor body formed on a substrate. Ohmic contacts are formed on the lower surface of the semiconductor body. In one embodiment, an insulating layer is formed over the Schottky and ohmic contacts and vias are formed in the insulating layer to the Schottky and ohmic contacts to form the anode and cathode electrodes. In another embodiment, vias are formed in the insulating layer to the Schottky contacts and vias are formed in the semiconductor body to the ohmic contacts. An anode electrode is formed in electrical contact with the Schottky contacts. A cathode electrode is formed in electrical contact with the ohmic contacts on the backside of the substrate.Type: ApplicationFiled: July 19, 2012Publication date: November 8, 2012Applicant: ALPHA & OMEGA SEMICONDUCTOR, INC.Inventor: TingGang Zhu
-
Patent number: 8305054Abstract: An energy control method for a inductive conversion device comprising: determination of individual error of multiple output voltages; determination of peak current based on the errors, determination of total energy through the peak current and charging to at least one inductor according to the peak current, whereas the inductor will store the total energy.Type: GrantFiled: January 13, 2010Date of Patent: November 6, 2012Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Ke-Horng Chen, Jean-Shin Wu, Yu-Nong Tsai, Ming-Yan Fan
-
Patent number: 8299494Abstract: A semiconductor device includes a first semiconductor layer and a second semiconductor layer of opposite conductivity type, a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches, and a second epitaxial layer of the second conductivity type formed on the first epitaxial layer where the second epitaxial layer is electrically connected to the second semiconductor layer. The first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, each having uniform doping concentration. The second epitaxial layer has a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration where the first and second thicknesses and the first doping concentration and second average doping concentrations are selected to achieve charge balance in operation.Type: GrantFiled: June 12, 2009Date of Patent: October 30, 2012Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
-
Patent number: 8288273Abstract: A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.Type: GrantFiled: October 17, 2011Date of Patent: October 16, 2012Assignee: Alpha & Omega Semiconductor Inc.Inventor: Il Kwan Lee
-
Patent number: 8288839Abstract: A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS.Type: GrantFiled: April 30, 2009Date of Patent: October 16, 2012Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla
-
Patent number: 8283212Abstract: A method for making a wire bond package comprising the step of providing a lead frame array comprising a plurality of lead frame units therein, each lead frame unit comprises a first die pad and a second die pad each having a plurality of tie bars connected to the lead frame array, a plurality of reinforced bars interconnecting the first and second die pads; the reinforced bars are removed after molding compound encapsulation.Type: GrantFiled: December 28, 2010Date of Patent: October 9, 2012Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Yan Xun Xue, Jun Lu, Anup Bhalla
-
Patent number: 8264084Abstract: A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes: a) Lithographically patterning the top metal layer into the contact zones and the contact enhancement zones. b) Forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.Type: GrantFiled: October 31, 2007Date of Patent: September 11, 2012Assignee: Alpha & Omega Semiconductor, Inc.Inventors: François Hébert, Anup Bhalla, Kai Liu, Ming Sun
-
Patent number: 8264861Abstract: A circuit is proposed for limiting maximum switching FET drain-source voltage (VDS) of a transformer-coupled push pull power converter with maximum DC supply voltage VIN—MAX. Maximum VDS is accentuated by leakage inductances of the push pull transformer and the power converter circuit traces. The limiting circuit bridges the drains of the switching FETs and it includes two serially connected opposing Zener diodes each having a Zener voltage Vzx. The invention is applicable to both N-channel and P-channel FETs. In a specific embodiment, Vzx is selected to be slightly ?2*VIN—MAX with the maximum VDS clamped to about VIN—MAX+½Vzx. In another embodiment, a proposed power switching device with integrated VDS clamping includes: In another embodiment, a proposed power switching device with integrated VDS-clamping includes a switching FET; and a Zener diode having a first terminal and a second terminal, the second terminal of the Zener diode is connected to the drain terminal of the switching FET.Type: GrantFiled: February 25, 2011Date of Patent: September 11, 2012Assignee: Alpha & Omega Semiconductor, Inc.Inventor: Sanjay Havanur
-
Patent number: 8258767Abstract: A power conversion system and power control method for reducing cross regulation effect uses a voltage feedback adjustment circuit to modulate an error signal fed back from an output voltage so as to predict the energy of an output corresponding to its load states. While the energy delivered to an output terminal with its load remaining the same does not change, the energy delivered to an output terminal with its load changing is adjusted accordingly. The power conversion system thus effectively reduces the cross regulation effect and obtains excellent steady system output and transient response.Type: GrantFiled: April 30, 2010Date of Patent: September 4, 2012Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Jean-shin Wu, Ke-Horng Chen
-
Patent number: 8253216Abstract: A gallium nitride based semiconductor diode includes a substrate, a semiconductor body including a first heavily doped GaN layer and a second lightly doped GaN layer. The semiconductor body includes mesas projecting upwardly from a lower surface where each of the mesas includes the second GaN layer and a portion of the first GaN layer. Schottky contacts are formed on the upper surface of the mesas and ohmic contacts are formed on the lower surface of the semiconductor body. An insulating layer is formed over the Schottky and ohmic contacts. Vias are formed in the insulating layer to the Schottky contacts and vias are formed in the semiconductor body to the Ohmic contacts. An anode electrode is formed in a first metal pad in electrical contact with the Schottky contacts. A cathode electrode is formed in a second metal pad in electrical contact with the ohmic contacts.Type: GrantFiled: July 26, 2011Date of Patent: August 28, 2012Assignee: Alpha and Omega Semiconductor, Inc.Inventor: TingGang Zhu
-
Patent number: 8252648Abstract: A power MOSFET device and manufacturing method thereof, includes the steps of selectively depositing a first conductive material in the middle region at the bottom of a contact trench and contacting with light-doped N-type epitaxial layer to form a Schottky junction and depositing a second conductive material at the side wall and bottom corner of the contact trench and contacting with P-type heavy-doped body region to form an ohmic junction. The first and second conductive materials can respectively optimize the performance of the ohmic contact and the Schottky contact without compromise. Meanwhile, the corner of the contact trench is surrounded by P-type heavy-doped region thereby effectively reducing the leakage currents accumulated at the corner of the contact trench.Type: GrantFiled: June 29, 2010Date of Patent: August 28, 2012Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Yeeheng Lee, Yongping Ding, John Chen
-
Patent number: 8247288Abstract: A bypass capacitor is directly integrated on top of a MOSFET chip. The capacitor comprises multi layers of conductive material and dielectric material staking on top of each other with connection vias through dielectric layer for connecting different conductive layers. The method of integrating the bypass capacitor comprises repeating steps of depositing a dielectric layer, forming connection vias through the dielectric layer, depositing a conductive layer and patterning the conductive layer.Type: GrantFiled: November 16, 2010Date of Patent: August 21, 2012Assignee: Alpha & Omega Semiconductor Inc.Inventors: Yan Xun Xue, Anup Bhalla, Hamza Yilmaz, Jun Lu
-
Patent number: 8247329Abstract: A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.Type: GrantFiled: February 9, 2011Date of Patent: August 21, 2012Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
-
Patent number: 8247297Abstract: A method is disclosed for creating a semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.Type: GrantFiled: December 15, 2009Date of Patent: August 21, 2012Assignee: Alpha & Omega Semiconductor Inc.Inventors: Xiaobin Wang, Anup Bhalla, Yeeheng Lee
-
Publication number: 20120205737Abstract: A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.Type: ApplicationFiled: April 26, 2012Publication date: August 16, 2012Applicant: ALPHA AND OMEGA SEMICONDUCTOR INCInventors: John Chen, Il Kwan Lee, Hong Chang, Wenjun Li, Anup Bhalla, Hamza Yilmaz
-
Patent number: 8242013Abstract: A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness TPSD. The FDC has patterned back-face carrier metallizations contacting the front-face device metallization pads, patterned front-face carrier metallization pads and numerous parallelly connected through-carrier conductive vias respectively connecting the back-face carrier metallizations to the front-face carrier metallization pads. The FDC thickness TFDC is large enough to provide structural rigidity to the VSLCPSD.Type: GrantFiled: March 30, 2010Date of Patent: August 14, 2012Assignee: Alpha & Omega Semiconductor Inc.Inventors: Tao Feng, Yueh-Se Ho
-
Patent number: 8236613Abstract: A method for wafer level chip scale package comprises providing a wafer with semiconductor chips formed thereon, forming a groove alongside each chip, providing a wafer size clip array with a plurality of clip contact areas each extending to a down set connecting bar, connecting the plurality of clip contact areas to a plurality of the electrodes disposed on a top surface of the chips with down set connecting bars disposed inside the grooves, encapsulating top of wafer in molding compound, thinning the bottom portion of the wafer and dicing the thin wafer into single chip packages. The chip has source and gate electrodes on a top surface connected to a first and second clip contact areas extending to a first a second down set connecting bars respectively, with the bottom surfaces of the down set connecting bars substantially coplanar to a drain electrode located at the chip bottom surface.Type: GrantFiled: May 24, 2010Date of Patent: August 7, 2012Assignee: Alpha & Omega Semiconductor Inc.Inventor: Yuping Gong
-
Publication number: 20120187481Abstract: A vertical trench LDMOS transistor includes a semiconductor layer of a first conductivity type; a first trench formed in the semiconductor layer and filled with a trench dielectric and a trench gate is formed in the first trench; a body region of a second conductivity type formed in the semiconductor layer adjacent the first trench; a source region formed in the body region and adjacent the first trench; a planar gate insulated from the semiconductor layer by a second gate dielectric layer and overlying the body region; and a drain drift region formed in the semiconductor layer. The planar gate forms a lateral channel in the body region between the source region and the drain drift region, and the trench gate in the first trench forms a vertical channel in the body region along the sidewall of the first trench between the source region and the semiconductor layer.Type: ApplicationFiled: April 5, 2012Publication date: July 26, 2012Applicant: Alpha & Omega Semiconductor, Inc.Inventor: Shekar Mallikarjunaswamy
-
Patent number: 8217748Abstract: An inductive power electronics package is disclosed. It has a circuit substrate with power inductor attached atop. The power inductor has inductor core of closed magnetic loop with an interior window. The closed magnetic loop can include air gap for inductance adjustment. The circuit substrate has bottom half-coil forming elements constituting a bottom half-coil beneath the inductor core. Also provided are top half-coil forming elements interconnected with the bottom half-coil forming elements to form an inductive coil enclosing the inductor core. An inner connection chip can be added in the interior window for interconnecting bottom half-coil forming elements with top half-coil forming elements. An outer connection chip can be added about the inductor core for interconnecting bottom half-coil forming elements with top half-coil forming elements outside the inductor core. A power Integrated Circuit can be attached to the top side of the circuit substrate as well.Type: GrantFiled: March 4, 2009Date of Patent: July 10, 2012Assignee: Alpha & Omega Semiconductor Inc.Inventors: Tao Feng, Xiaotian Zhang, François Hébert, Ming Sun
-
Patent number: 8217503Abstract: A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.Type: GrantFiled: September 14, 2010Date of Patent: July 10, 2012Assignee: Alpha & Omega Semiconductor Inc.Inventors: Yueh-Se Ho, Yan Xun Xue, Jun Lu