Abstract: A flyback converter to control conduction time in AC/DC conversion technology. The flyback converter includes a primary side and a secondary side. The primary side includes a main switch connecting a primary coil to the input of the flyback converter in series. The secondary side includes a secondary coil coupling with the output terminal of the flyback converter. When a switching frequency of the main switch is at a preset first on time in the range between the off frequency and the second switching frequency, the on-time of the main switch continuously changes corresponding to output load changes. When the switching frequency of the main switch is higher than the first switching frequency, the on time of the main switch is constant. The on time is controlled to change linearly, so as to avoid excessive changes in the output voltage ripples, thereby improving circuit efficiency.

Abstract: A wafer level chip scale semiconductor package comprises a device semiconductor layer, a backside metallization layer, a film laminate layer, and a metal layer. The device semiconductor layer comprises a plurality of metal electrodes disposed on a front surface of the device semiconductor. Each side surface of the backside metallization layer is coplanar with a corresponding side surface of the device semiconductor layer. Each side surface of the metal layer is coplanar with a corresponding side surface of the film laminate layer. A surface area of a back surface of the backside metallization layer is smaller than a surface area of a front surface of the metal layer.

Abstract: A method comprises the steps of providing a wafer; applying a redistribution layer, grinding a back side of the wafer; depositing a metal layer; and applying a singulation process. A semiconductor package comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), a redistribution layer, and a metal layer. The MOSFET comprises a source electrode, a gate electrode, a drain electrode and a plurality of partial drain plugs. The source electrode, the gate electrode, and the drain electrode are positioned at a front side of the MOSFET.

Abstract: A flyback converter, including: a transformer, a first switch, a second switch, and a control circuit. The transformer includes a first side and a second side. The first switch is coupled to the first side at an input terminal. The second switch is coupled to the second side and an output terminal. The control circuit is coupled between the output terminal and the second switch, wherein the control circuit is arranged to adjust a voltage on the input terminal by changing a flow of a current between the second switch and the second side.

Abstract: A semi-wafer level packaging method comprises the steps of providing a wafer; grinding a back side of the wafer; forming a metallization layer; removing a peripheral ring; bonding a first tape; applying a dicing process; bonding a second tape; removing the first tape; bonding a supporting structure; bonding a third tape; removing the second tape; and applying a singulation process. A semi-wafer level packaging method comprises the steps of providing a wafer; attaching a carrier wafer to the wafer; grinding a back side of the wafer; forming a metallization layer; applying a dicing process; bonding a supporting structure; removing the carrier wafer; bonding a tape; and applying a singulation process.

Abstract: An intelligent power module (IPM) comprises a first, second, third and fourth die supporting elements, a first group of insulated gate bipolar transistors (IGBTs), a second group of IGBTs, a first group of super-junction metal-oxide-semiconductor field-effect transistors (MOSFETs), a second group of super-junction MOSFETs, a fifth die supporting element, a low voltage IC, a high voltage IC, and a molding encapsulation. The low and high voltage ICs are attached to the fifth die supporting element. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first group of IGBTs, the second group of IGBTs, the first group of super-junction MOSFETs, the second group of super-junction MOSFETs, the fifth die supporting element, the low voltage IC, the high voltage IC.

Abstract: Apparatus and associated methods relate to dynamic bandwidth control of a variable frequency modulation circuit by selective contribution of a crossover frequency tuning engine (XFTE) in response to a transient in a switching frequency. In an illustrative example, the XFTE may generate a transient control signal (Ctrans) in response to a transient in a control output signal trans, (Cout) indicative of switching frequency and received from a feedback control circuit. The XFTE may generate Ctrans, for example, according to a predetermined relationship between a crossover frequency and the switching frequency of the modulation circuit. The feedback control circuit may, for example, generate Cout from a predetermined reference and a control input signal. Cout may, for example, correspond to a pulse-width modulated output delivered to a load through an inductor.

Abstract: When a constant on-time flyback converter is in the switch-on stage, the gate voltage of the switch and the input voltage of the flyback converter adopt the primary side of the transformer to control. The gate voltage is controlled by the second control signal generated by the controller. The flyback converter is then turn off to enter the switch off stage. When the flyback converter is in the switch off stage, the secondary side controller on the secondary side of the transformer, based on the output voltage and output current of the secondary side, sends a first control signal to the primary side controller to control the main switch to turn on. Thus, the flyback converter enters the switch-on stage. Therefore, the calculation complexity is reduced, and there is no need to set a blanking time, such that the flyback converter can be used in high switching frequency applications.

Abstract: A semiconductor package comprises a lead frame, a low side metal-oxide-semiconductor field-effect transistor (MOSFET), an E-fuse MOSFET, a high side MOSFET, a metal connection, a gate driver, an E-fuse IC, and a molding encapsulation. A buck converter comprises a smart power stage (SPS) network and an E-fuse solution network. The SPS network comprises a high side switch, a low side switch, and a gate driver. A drain of the low side switch is coupled to a source of the high side switch via a switch node. The gate driver is coupled to a gate of the high side switch and a gate of the low side switch. The E-fuse solution network comprises a sense resistor, an E-fuse switch, an E-fuse integrated circuit (IC), and an SD circuit.

Abstract: A semi-wafer level packaging method comprises the steps of providing a wafer; grinding a back side of the wafer; forming a metallization layer; removing a peripheral ring; bonding a first tape; applying a dicing process; bonding a second tape; removing the first tape; bonding a supporting structure; bonding a third tape; removing the second tape; and applying a singulation process. A semi-wafer level packaging method comprises the steps of providing a wafer; attaching a carrier wafer to the wafer; grinding a back side of the wafer; forming a metallization layer; applying a dicing process; bonding a supporting structure; removing the carrier wafer; bonding a tape; and applying a singulation process.

Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles, a first plurality of leads, and a second plurality of leads. A respective end surface of each lead of the first plurality of leads and the second plurality of leads is plated with a metal. A first respective window on a first side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A second respective window on a second side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A method for fabricating a semiconductor package comprises the steps of providing a lead frame array, mounting a chip, forming a molding encapsulation, and applying a cutting process or a punching process.

Abstract: Apparatus and associated methods relate to a power supply noise disturbance rejection circuit (NDRC) having a first circuit reference potential (CRP1), a second circuit reference potential (CRP2), and a galvanic link conductively connecting CRP1 and CRP2 and providing a non-zero resistance return path for at least one current mode signal (CMS). In an illustrative example, a power supply monitor circuit (PSMC) may be referenced to CRP1 and a control circuit to CRP2. The PMSC may, for example, generate a voltage mode signal (VMS) relative to CRP1 and representing an output parameter of a power supply circuit (PSC), and convert the VMS into a first CMS (CMS1). The control circuit may, for example, generate a control signal for the PSC from CMS1. Various embodiments may advantageously attenuate a noise margin of a CMS presented at the control circuit by a factor of at least 10 relative to an equivalent VMS.

Abstract: A power stage in a multi-phase switching power supply incorporates a current sense transistor coupled in series with the output inductor to sense the phase current for the power stage. In some embodiments, the current sense transistor mirrors the output voltage disconnect transistor (the ORing FET) used to switchably connect a power stage to the output voltage node. The current sense transistor measures a portion of the inductor current flowing through the output inductor where the inductor current is indicative of the phase current of the power stage. Accurate current sensing is implemented for the power stage where the current sense value dose not require temperature compensation.

Abstract: A flyback converter includes a transformer, a sensing impedance, a switch and a control circuit. The sensing impedance is coupled between the transformer and an output terminal of the flyback converter. The switch is coupled to the transformer. The transformer is charged when the switch activates. The transformer is discharged when the switch deactivates. The control circuit is arranged to detect if the sensing impedance is bypassed, and further arranged to adjust an operating frequency of the switch when the sensing impedance is bypassed.

Abstract: An isolated converter has a constant voltage mode and a constant current mode. The isolated converter includes a transformer, a main switch, a driver, a controller, and an isolator. The controller includes a constant current control unit, a voltage comparator, and a control logic unit. The constant current control unit generates a voltage adjustment signal to adjust the reference voltage or voltage feedback signal according to a current feedback signal for sensing the output current. The control logic unit generates a trigger signal according to the comparison signal of the voltage comparator. The isolator connects the output terminal of the controller and the driver. The input terminal is used to transmit the trigger signal to the input terminal of the driver. The isolated converter can provide excellent constant voltage transient response and stable constant current regulation according to load conditions by improving the controller.

Abstract: A port controller circuit implements monitoring and detection of power path short failures by regulating the control voltage to the power switches during the on-state of the power switches. A failure condition is indicated when the control voltage to a power switch is regulated to a voltage level outside of a permissible range. The port controller circuit implements real-time monitoring where a short within the power path can be detected while the power path is enabled and the fault condition can be used to disable other port controller circuits in a multi-port system. In one embodiment, a port controller circuit includes a pair of back-to-back transistors forming the power path and the real-time fault detection scheme is applied to control each transistor independently to determine if either transistor has a fault condition.

Abstract: Apparatus and associated methods relate to implementing an auto-inductance-detection architecture to reconstruct current monitor output (IMON) when a low-side switch in a power stage is on. In an illustrative example, an IMON generation circuit may include a variable resistor. A close loop control (e.g., OTA, switches, and variable resistor) may be configured to adjust a resistance value of the variable resistor automatically. The IMON generation circuit may also include a low pass filter coupled to a switching node of the power stage to receive a corresponding signal and provide a DC value. The difference between the corresponding signal and the DC value may be configured to enable or disable the close loop control. By providing the close loop control, the IMON generation circuit may advantageously perform auto-inductance detection (AID) and provide a more accurate IMON reconstruction method.

Abstract: A semiconductor package fabrication method comprises the steps of providing a wafer, applying a seed layer, forming a photo resist layer, plating a copper layer, removing the photo resist layer, removing the seed layer, applying a grinding process, forming metallization, and applying a singulation process. A semiconductor package comprises a silicon layer, an aluminum layer, a passivation layer, a polyimide layer, a copper layer, and metallization. In one example, an area of a contact area of a gate clip is smaller than an area of a gate copper surface. The area of the contact area of the gate clip is larger than a gate aluminum surface. In another example, an area of a contact area of a gate pin is larger than an area of a gate copper surface. The area of the contact area of the gate pin is larger than a gate aluminum surface.

Abstract: A semiconductor package fabrication method comprises the steps of providing a wafer, applying a seed layer, forming a photo resist layer, plating a copper layer, removing the photo resist layer, removing the seed layer, applying a grinding process, forming metallization, and applying a singulation process. A semiconductor package comprises a silicon layer, an aluminum layer, a passivation layer, a polyimide layer, a copper layer, and metallization. In one example, an area of a contact area of a gate clip is smaller than an area of a gate copper surface. The area of the contact area of the gate clip is larger than a gate aluminum surface. In another example, an area of a contact area of a gate pin is larger than an area of a gate copper surface. The area of the contact area of the gate pin is larger than a gate aluminum surface.

Abstract: A multi-port system and method implements fault detection using a resistor connected to each port controller where the resistors of at least two port controllers are connected together in parallel. Each port controller supplies a predetermined current to the associated resistor and senses the resistor voltage of the parallelly connected resistors to detect for a fault condition. A failure condition is indicated when the resistor voltage is outside of a given threshold window. In this manner, for a single point failure, such as a short along the power path of a port controller, the other port controller senses a change in the resistor voltage and can assert a fault signal. In one embodiment, the fault signal is an open drain output and operates to pull down on a fault bus, which disables all the port controllers in the system through a disable input.