Abstract: Epitaxial lift off systems and methods are presented. In one embodiment a tape is disposed on the opposite side of the epitaxial material than the substrate is used to hold the epitaxial material during the etching and removal steps of the ELO process. In various embodiments, the apparatus for removing the ELO film from the substrates without damaging the ELO film may include an etchant reservoir, substrate handling and tape handling mechanisms, including mechanisms to manipulate (e.g., cause tension, peel, widen the etch gap, etc.) the lift off component during the lift off process.

Abstract: Embodiments of the invention generally relate to apparatuses for chemical vapor deposition (CVD) processes. In one embodiment, a heating lamp assembly for a vapor deposition reactor system is provided which includes a lamp housing disposed on an upper surface of a support base and containing a first lamp holder and a second lamp holder and a plurality of lamps extending from the first lamp holder to the second lamp holder. The plurality of lamps may have split filament lamps and/or non-split filament lamps, and in some examples, split and non-split filament may be alternately disposed between the first and second lamp holders. A reflector may be disposed on the upper surface of the support base between the first and second lamp holders. The reflector may contain gold or a gold alloy.

Abstract: A substrate processing system architecture includes an MOCVD reactor processing module coupled to a single three-level load lock chamber. The load lock has a heater at a first stationary location, a cold plate at a second secondary location, and a three-level transport system between the heater and cold plate. The transport system has two-position carrier transfer assembly with upper and lower stages, where the upper stage may move between an intermediate transfer level and an upper level proximate to the heater while the lower stage moves between a lower level proximate to the cold plate and the transfer level. The choreography of substrate transport between external loader, load lock and reactor allows substrates to be processed in the reactor while other substrates are post-process cooled, unloaded, and a new substrate loaded and preheated.

Abstract: A method for separation of semiconductor device cell units from fabricated large-area cell units, together with a corresponding tile unit structure, are provided in which the tile unit is cut along cell unit boundaries while leaving intact a set of specified tab sections distributed along the cell unit boundaries. The tile unit may be a multi-layer composite of a semiconductor layer with a conductive metallic base supported upon a polymer layer and adhered thereto by an adhesive film, wherein tab sections are cut completely through the semiconductor layer and its metallic base from above and may also be cut partially through the polymer layer from below, leaving at least a portion of the polymer layer in place at tab sections. Tile units can be handled such that component cell units are held together by the tab sections, until a physical final separation of selected cell units.

Abstract: A fastener system and method for supporting and retaining modular insulating quartz liners with gas apertures in close proximity to corresponding apertures in diffusers of gas showerheads. Tubular fasteners have a head, a tubular shank and a foot that extend through a liner plate nozzle into a diffuser plate. A keyway in the gas diffuser, aligned and coaxial with a diffuser nozzle, allows the foot to reach an arcuate concourse through a keyway where it can be locked by bayonet turning. The keyway is machined into the diffuser by EDM and is an inversion of the fastener tip geometry rotated about the axis of the tubular shank. Each fastener and nozzle set form a coaxial path for distributing processing gas to substrates through liner and diffuser plates from a plenum in showerheads of a MOCVD reactor.

Abstract: A method for providing a textured layer in an optoelectronic device is disclosed. The method includes depositing a template layer on a first layer. The template layer has significant inhomogeneity either in thickness or in composition, or both, including the possibility of forming one or more islands to provide at least one textured surface of the island layer. The method also includes exposing the template layer and the first layer to an etching process to create or alter at least one textured surface. The altered at least one textured surface is operative to cause scattering of light.

Abstract: A showerhead for a semiconductor processing reactor formed by an array of showerhead tiles. Each showerhead tile has a plurality of process gas apertures, which may be in a central area of the tile or may extend over the entire tile. Each showerhead tile can be dimensioned for processing a respective substrate or a plurality of substrates or the array can be dimensioned for processing a substrate. An exhaust region surrounds the process gas apertures. The exhaust region has at least one exhaust aperture, and may include an exhaust slot, a plurality of connected exhaust slots or a plurality of exhaust apertures. The exhaust region surrounds the array of showerhead tiles, or a respective portion of the exhaust region surrounds the plurality of process gas apertures in each showerhead tile or group of showerhead tiles. A gas curtain aperture may be between the exhaust region and the process gas apertures of one of the showerhead tiles or adjacent to the central area of the tile.

Abstract: A chemical vapor deposition reactor has one or more deposition zones bounded by gas flow virtual walls, within a housing having closed walls. Each deposition zone supports chemical vapor deposition onto a substrate. Virtual walls formed of gas flows laterally surround the deposition zone, including a first gas flow of reactant gas from within the deposition zone and a second gas flow of non-reactant gas from a region laterally external to the deposition zone. The first and second gas flows are mutually pressure balanced to form the virtual walls. The virtual walls are formed by merging of gas flows at the boundary of each deposition zone. The housing has an exhaust valve to prevent pressure differences or pressure build up that would destabilize the virtual walls. Cross-contamination is reduced, between the deposition zones and the closed walls of the housing or an interior region of the housing outside the gas flow virtual walls.

Abstract: A showerhead for a semiconductor-processing reactor formed by an array of showerhead tiles. Each showerhead tile has a plurality of process gas apertures, which may be in a central area of the tile or may extend over the entire tile. Each showerhead tile can be dimensioned for processing a respective substrate or the array can be dimensioned for processing a substrate. An exhaust region surrounds the process gas apertures. The exhaust region has at least one exhaust aperture, and may include an exhaust slot, a plurality of connected exhaust slots or a plurality of exhaust apertures. The exhaust region surrounds the array of showerhead tiles, or a respective portion of the exhaust region surrounds the plurality of process gas apertures in each showerhead tile or group of showerhead tiles. A gas curtain aperture may be between the exhaust region and the process gas apertures of one of the showerhead tiles or adjacent to the central area of the tile.

Abstract: Embodiments generally relate to optoelectronic semiconductor devices such as photovoltaic cells. In one aspect, a method for forming a device includes forming an absorber layer made of gallium arsenide (GaAs) and having one type of doping, and forming an emitter layer made of a different material and having a higher bandgap than the absorber layer. An intermediate layer can be formed between emitter and absorber layers. A heterojunction and p-n junction are formed between the emitter layer and the absorber layer, where the p-n junction is formed at least partially within the different material at a location offset from the heterojunction. A majority of the absorber layer can be outside of a depletion region formed by the p-n junction. The p-n junction causes a voltage to be generated in the cell in response to the cell being exposed to light at a front side.

Abstract: Embodiments of the invention generally relate to apparatuses for chemical vapor deposition (CVD) processes. In one embodiment, a wafer carrier track for levitating and traversing a wafer carrier within a vapor deposition reactor system is provided which includes upper and lower sections of a track assembly having a gas cavity formed therebetween. A guide path extends along an upper surface of the upper section and between two side surfaces which extend along and above the guide path and parallel to each other. A plurality of gas holes along the guide path extends from the upper surface of the upper section, through the upper section, and into the gas cavity. In some examples, the upper and lower sections of the track assembly may independently contain quartz, and in some examples, may be fused together.

Abstract: An apparatus or method for forming a tape-based, epitaxial lift-off film. The epitaxial lift-off film can be for at least one of a solar device, a semiconductor device, and an electronic device. The apparatus can comprise: a tape supply section, the tape supply section providing an unloaded support tape; a lamination section for receiving the unloaded support tape and a plurality of substrates, each substrate containing an epitaxial film thereon, the lamination section adhering the substrates to the unloaded support tape to form a loaded support tape; and an ELO etch section comprising a pressure system for applying pressure on said loaded support tape such that pressure is applied progressively downward and progressively towards a center-line of said loaded support tape when passing through said ELO etch section, the ELO etch section removing the substrates from the loaded support tape, while leaving the epitaxial film on the loaded support tape.

Abstract: An apparatus, system and method for performing ELO are disclosed. Device assemblies are contemporaneously etched in a stacked arrangement. Each device assembly may be placed in a respective tray, where the trays are overlapped and spaced apart from one another. In this manner, more device assemblies can be etched per unit area compared to conventional systems. Further, by stacking device assemblies during etching, the yield can be improved and/or the cost of the etch tank and associated hardware can be reduced.

Abstract: Embodiments generally relate to optoelectronic semiconductor devices such as solar cells. In one aspect, a device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device and is made of a different material and having a higher bandgap than the absorber layer. A heterojunction is formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. An intermediate layer is located between the absorber layer and the emitter layer and provides the offset of the p-n junction from the heterojunction, and includes a graded layer and an ungraded back window layer.

Abstract: Embodiments generally relate to optoelectronic devices and more specifically, to textured layers in optoelectronic devices. In one embodiment, a method for providing a textured layer in an optoelectronic device includes depositing a first layer of a first material and depositing an island layer of a second material on the first layer. Depositing the island layer includes forming one or more islands of the second material to provide at least one textured surface of the island layer, where the textured surface is operative to cause scattering of light.

Abstract: Embodiments generally relate to optoelectronic semiconductor devices such as photovoltaic cells. In one aspect, a method for forming a device includes forming an absorber layer made of gallium arsenide (GaAs) and having one type of doping, and forming an emitter layer made of a different material and having a higher bandgap than the absorber layer. An intermediate layer can be formed between emitter and absorber layers. A heterojunction and p-n junction are formed between the emitter layer and the absorber layer, where the p-n junction is formed at least partially within the different material at a location offset from the heterojunction. A majority of the absorber layer can be outside of a depletion region formed by the p-n junction. The p-n junction causes a voltage to be generated in the cell in response to the cell being exposed to light at a front side.

Abstract: A method of assembling a matrix of photovoltaic cells includes positioning photovoltaic cells in a desired orientation, aligning the row of photovoltaic cells relative to each other, and enabling a homogeneous downward pressure on the row of photovoltaic cells to facilitate electrical and mechanical connectivity between the photovoltaic cells.

Abstract: A method and apparatus for performing chemical vapor deposition (CVD) processes is provided. In one embodiment, the apparatus comprises a reactor body having a processing region, comprising a wafer carrier track having a wafer carrier disposed thereon, at least one sidewall having an exhaust assembly for exhausting gases from the processing region, a lid assembly disposed on the reactor body, comprising a lid support comprising a first showerhead assembly for supplying reactant gases to the processing region, a first isolator assembly for supplying isolation gases to the processing region, a second showerhead assembly for supplying reactant gases to the processing region, and a second isolator assembly for supplying isolation gases to the processing region, wherein the first showerhead assembly, the first isolator assembly, the second showerhead assembly, and the second isolator assembly are consecutively and linearly disposed next to each other.

Abstract: Embodiments of the invention generally relate to a concentric gas manifold assembly used in deposition reactor or system during a vapor deposition process. In one embodiment, the manifold assembly has an upper section coupled to a middle section coupled to a lower section. The middle section contains an inlet, a manifold extending from the inlet to a passageway, and a tube extending along a central axis and containing a channel along the central axis and in fluid communication with the passageway. The lower section of the manifold assembly contains a second manifold extending from a second inlet to a second passageway and an opening concentric with the central axis. The tube extends to the opening to form a second channel between the tube and an edge of the opening. The second channel is concentric with the central axis and is in fluid communication with the second passageway.

Abstract: A fixture for cutting thin substrates, such as films, wafers, semiconductor layers and the like, using a blade holder assembly joined to a substrate clamp assembly. Each assembly has a plurality of members with the substrate clamp having a base plate that introduces a vacuum environment and a substrate support plate that uses the vacuum to secure the substrate in place. The blade holder assembly has interlocking projections in interleaving sheet members sandwiched between two bracket members that define slots for supporting a knife. Multiple slots allow the blade to be positioned in different positions and different orientations for cutting thin substrates held with vacuum pressure in the substrate clamp assembly.