Abstract: Various technologies described herein pertain to defect pixel correction for image data collected by a pixel array of an image sensor. Neighborhood statistics for a given pixel from the image data are computed based on values of neighbor pixels of the given pixel from the image data. Whether the value of the given pixel is defective is detected based on the neighborhood statistics. The value of the given pixel is replaced when detected to be defective to output modified image data. Correction of the given pixel is a function of whether the given pixel is in a flat region or a non-flat region. When the given pixel is defective and in a non-flat region, a minimum edge across the given pixel is identified and the value of the given pixel is replaced with an average of values of neighbor pixels that belong to the minimum edge.

Abstract: Providing for operation of high-speed optical sensor equipment at full data path speeds in conjunction with testing equipment operating at a lower speed is described herein. By way of example, a data stream output from optical sensor equipment to testing equipment can be throttled at a serial interface between such equipment. Throttling can involve subdividing a set of pixel data and outputting a subset of the pixel data in a given readout frame. Consecutive outputs of respective subsets of pixel data are initiated with an offset from the previous readout frame. Accordingly, the optical sensor equipment can be operated at full speeds, simulating realistic operational conditions, while slower testing equipment can be utilized to perform data analytics, heuristics, and other quality tests on various portions of the optical sensor equipment.

Abstract: A method for correcting column Fixed Pattern Noise (FPN) in an image sensor offers a compromise between speed and precision for calculating column FPN offsets. The present correction technique is digital, and is applied after the pixel signal voltages have been digitized by an ADC. A first Optical Black (OB) pixel is sampled and compared to a target level. An offset is stored, and an appropriate push-size is determined. Additional OB pixels are sampled and the offset is applied. The push-size is increased or decreased depending upon whether the pixel signal with the applied offset is above or below a target value. This new offset value is written to memory, and the push-size is reduced, and the process is repeated until the last OB pixel has been processed. The resulting offset is applied to the signal pixels in a column.

Abstract: The claimed subject matter provides systems and/or methods that facilitate combining analog and digital gain for utilization with CMOS sensor imagers. The analog gain can provide coarse gain steps and the digital gain can provide finer gain steps between adjacent coarse analog gain values. Further, since analog gain can suffer from low precision, dispersion, etc., on-chip calibration can be implemented to calibrate the analog and digital gain. For example, a digital amplifier can be calibrated to compensate for differences between actual and nominal analog gains associated with one or more analog amplifiers.

Abstract: Providing for analog averaging of optical black pixels of an image sensor is described herein. By way of example, optical black pixel signals can be output by a row of pixels and provided in a parallel manner to a readout circuit. The readout circuit can include an averaging circuit that, when activated, generates an analog average of signals received at the readout circuit. The analog average can be sampled at any suitable signal output of the readout circuit, or multiple samples can be acquired to mitigate temporal noise, improve yield, and so on. By utilizing analog averaging, optical black pixel information can be obtained much more quickly than with digital counterparts, and optical black pixels can be fully utilized, as well as utilized more flexibly, in generating the black pixel output. Further sensor die size can be reduced, by replacing digital adders, dividers or shifters with the averaging circuit.

Abstract: An image sensor architecture provides an SNR in excess of 100 dB, without requiring the use of a mechanical shutter. The circuit components for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer is preferably manufactured using a low-noise PMOS manufacturing process, and includes the photodiode and amplifier circuitry for each pixel. A bottom layer is preferably manufactured using a standard CMOS process, and includes the NMOS pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a PMOS process to optimized for forming low-noise pixels, the pixel performance can be greatly improved, compared to using CMOS. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a standard CMOS process, which has been optimized for circuit speed and manufacturing cost.

Abstract: Providing for a two-stage single-slope analog to digital converter (ADC) exhibiting high resolution in conjunction with reduced power consumption is described herein. The ADC can achieve a digital resolution of at least 13 bits according to one or more disclosed embodiments, with significantly lower power consumption than conventional high resolution analog to digital converters. In operation, bias current supplied to one or more components of the ADC can be ramped up to a high magnitude during high accuracy or high speed processes of the ADC. Upon completion of these processes, the bias current can be sharply reduced for at least a portion of a clock cycle. During a residue amplification process associated with a second stage of the ADC, bias current can be increased to a moderate level. Average power consumption can be reduced significantly, while maintaining peak power requirements.

Abstract: Programmable data readout for optical image sensors is disclosed herein. By way of example, vertical skipping and vertical mixing functionality is provided that is responsive to commands, enabling dynamic selectivity and processing of optical sensor data. A data output control system can be incorporated with or coupled to data readout circuitry of an optical sensor. The output control system comprises a vertical skipping engine that can dynamically select a subset of data for output in response to one or more skipping commands, and a vertical mixing engine that can act upon subsets of data in accordance with processing functions called by respective mixing commands. The disclosure provides simplification of selective data readout and processing for image sensors, potentially reducing design, testing, and maintenance overhead, as well as cost and number of integrated circuit components.

Abstract: The claimed subject matter provides systems and/or methods that facilitate mitigating an impact resulting from mismatch between signal chains in a CMOS imaging System-on-Chip (iSoC) sensor. Two-by-two pixel structures can be a basic building block upon which a pixel array is constructed. Further, each two-by-two pixel structure can be associated with a read bus that carries a sampled signal to a top end and a bottom end of a chip. Moreover, multiplexers at either end of the chip can select a subset of the read buses from which to receive a subset of the sampled signals. Accordingly, pixels in a first color plane can be read, processed, etc. on the same side of the chip (e.g., utilizing a common signal chain), while pixels in at least one second color plane can be read, processed, etc. on the other side of the chip (e.g., employing a differing signal chain).

Abstract: An image sensor, system and method that alternates sub-sets of pixels with long exposure times and pixels with short exposure times on the same sensor to provide a sensor having improved Wide Dynamic Range (WDR). The sub-sets of pixels are reset at different time intervals after being read, which causes the respective integration times to vary. By combining information contained in the both the short and long integration pixels, the dynamic range of the sensor is improved.

Abstract: Various technologies described herein pertain to automatically adjusting the strength of a voltage booster of an image sensor. A self-scaled voltage booster includes a regulator, a controller, and two or more charge pumps that can be selectively enabled and disabled by the controller. The controller generates controller signals for the charge pumps based on a duty cycle of a regulator signal generated by the regulator. Moreover, the controller can maintain the controller signals without modification for at least a predetermined minimum period of time after a prior modification of at least one of the controller signals. Further, the controller can include a duty cycle and delay module (or a plurality of duty cycle and delay modules) that detects the duty cycle of the regulator signal and maintains the controller signals without modification for at least the predetermined minimum period of time.

Abstract: Providing for a two-stage single-slope analog to digital converter (ADC) exhibiting high resolution in conjunction with reduced power consumption is described herein. The ADC can achieve a digital resolution of at least 13 bits according to one or more disclosed embodiments, with significantly lower power consumption than conventional high resolution analog to digital converters. In operation, bias current supplied to one or more components of the ADC can be ramped up to a high magnitude during high accuracy or high speed processes of the ADC. Upon completion of these processes, the bias current can be sharply reduced for at least a portion of a clock cycle. During a residue amplification process associated with a second stage of the ADC, bias current can be increased to a moderate level. Average power consumption can be reduced significantly, while maintaining peak power requirements.

Abstract: Aspects relate to improved optically black reference pixels in a CMOS iSoc sensor. A system can include a pointer P1 that indicates pixels to be read out during a readout time interval, a pointer P2 that indicates pixels to be reset during the time interval, and a pointer P3 that preserves a validity of a frame. The system also includes a pointer P4 configured to mitigate an integration time of column fixed pattern noise (FPN) rows independently of the integration time of other rows. In some aspects, pointer P4 can mitigate blooming into sampled rows from surrounding rows. Pointer P4 can be continuously rotated, in an aspect. Further, in some aspects, pointer P4 can jump on a second cycle to arrive one line before pointer P1.

Abstract: Systems and methods are provided that facilitate employing a plurality of independent reset buses for a column of pixels in a pixel array of a CMOS sensor imager. Utilization of the plurality of independent reset buses for the column of pixels can enable independent reset to be effectuated when employing sub-frame integration. For example, rows to be read and reset during a given readout time interval can be selected based upon one or more criteria. Further, each of the rows selected during the given readout time interval can be associated with a respective distinct reset bus. By leveraging the plurality of independent reset buses, uniformity in pixel operation can be maintained whether operating in full frame integration mode or sub-frame integration mode. Thus, noise resultant from changing between integration modes can be mitigated by using the plurality of independent reset buses.

Abstract: Systems and methods are provided to implement a state map to control operations of a complementary metal-oxide-semiconductor (CMOS) sensor. The state map can be a table comprising one or more locations. Each of the locations can comprise a destination state to define the operations of the sensor and an exit criterion to advance to a next location in the state map. For example, an operation sequence can be implemented using the state map to instruct the CMOS sensor to perform a specific set of operations. Further, a data value to represent the destination state and/or a variable input can be stored in a writable address of a register. Thus, a simplified architecture can be provided to implement CMOS sensor operation states, for instance, to improve interactions between real time and non-real time signals and to increase functionality of the CMOS sensor.

Abstract: Various technologies described herein pertain to automatically adjusting the strength of a voltage booster of an image sensor. A self-scaled voltage booster includes a regulator, a controller, and two or more charge pumps that can be selectively enabled and disabled by the controller. The controller generates controller signals for the charge pumps based on a duty cycle of a regulator signal generated by the regulator. Moreover, the controller can maintain the controller signals without modification for at least a predetermined minimum period of time after a prior modification of at least one of the controller signals. Further, the controller can include a duty cycle and delay module (or a plurality of duty cycle and delay modules) that detects the duty cycle of the regulator signal and maintains the controller signals without modification for at least the predetermined minimum period of time.

Abstract: Programmable data readout for optical image sensors is disclosed herein. By way of example, vertical skipping and vertical mixing functionality is provided that is responsive to commands, enabling dynamic selectivity and processing of optical sensor data. A data output control system can be incorporated with or coupled to data readout circuitry of an optical sensor. The output control system comprises a vertical skipping engine that can dynamically select a subset of data for output in response to one or more skipping commands, and a vertical mixing engine that can act upon subsets of data in accordance with processing functions called by respective mixing commands. The disclosure provides simplification of selective data readout and processing for image sensors, potentially reducing design, testing, and maintenance overhead, as well as cost and number of integrated circuit components.

Abstract: Aspects describe front-end pixel fixed pattern noise correction in imaging arrays having wide dynamic range. A photosensor of a first pixel in a first row of an array is reset and a first reset level of the first pixel is measured. The array comprises a plurality of pixels arranged in rows and columns. In response to a result of the first reset level, a reset bus is altered. A feed-forward adjustment of the photosensor of the first pixel is performed to substantially remove fixed-pattern noise. An external readout from the photosensor can occur with substantially all the fixed-pattern noise removed. In some aspects, the adjustment is performed by a switched capacitor block.

Abstract: Providing for pausing data readout from an optical sensor array is described herein. By way of example, an interruption period can be introduced into a readout cycle of the optical sensor array to suspend readout of data. During the interruption period, other operations related to the optical sensor array can be performed, including operations that are typically detrimental to image quality. Moreover, these operations can be performed while mitigating or avoiding negative impact on the image quality. Thus, greater flexibility is provided for global shutter operations, for instance, potentially improving frame rates and fine control of image exposure, while preserving image quality.

Abstract: Systems and methods are provided that facilitate staggering resets of rows of pixels in a CMOS imaging iSoC sensor. Reset signals and select signals can be provided to pixels in a pixel array in a coordinated manner when employing full frame integration or sub-frame integration. Further, reset signals and select signals can be transferred to a first row of pixels, while reset signals can be transferred to a second row of pixels during a unique readout time interval when utilizing sub-frame integration. Within the unique readout time interval, reset signals can be transferred to the first row of pixels during a first time period, while reset signals can be transferred to the second row of pixels during a second time period, where the first and second time periods are non-overlapping. Accordingly, cross-talk between rows of pixels during reset can be mitigated, which leads to enhanced uniformity.