Abstract: A self-balanced diode device includes a substrate, a doped well, at least one first conductivity type heavily doped fin and at least two second conductivity type heavily doped fins. The doped well is arranged in the substrate. The first conductivity type heavily doped fin is arranged in the doped well, arranged in a line along a first direction, and protruded up from a surface of the substrate. The second conductivity type heavily doped fins is arranged in the doped well, arranged in a line along a second direction intersecting the first direction, respectively arranged at two opposite sides of the first conductivity type heavily doped fin, and protruded up from the surface of the substrate. Each second conductivity type heavily doped fin and the first conductivity type heavily doped fin are spaced at a fixed interval.

Abstract: A self-balanced diode device includes a substrate, a doped well, at least one first conductivity type heavily doped fin and at least two second conductivity type heavily doped fins. The doped well is arranged in the substrate. The first conductivity type heavily doped fin is arranged in the doped well, arranged in a line along a first direction, and protruded up from a surface of the substrate. The second conductivity type heavily doped fins is arranged in the doped well, arranged in a line along a second direction intersecting the first direction, respectively arranged at two opposite sides of the first conductivity type heavily doped fin, and protruded up from the surface of the substrate. Each second conductivity type heavily doped fin and the first conductivity type heavily doped fin are spaced at a fixed interval.

Abstract: A self-balanced silicon-controlled rectification device includes a substrate, an N-type doped well, a P-type doped well, at least one heavily doped clamping fin, at least one first P-type heavily doped fin, and at least one first N-type heavily doped fin. The N-type doped well and the P-type doped well are arranged in the substrate. The heavily doped clamping fin is arranged in the N-type doped well and the P-type well and protruded up from a surface of the substrate. The first P-type heavily doped fin and the first N-type heavily doped fin are respectively arranged in the N-type doped well and the P-type doped well, and protruded up from the surface of the substrate. The abovementioned elements forms silicon-controlled rectifiers (SCRs) are forward biased to generate uniform electrostatic discharge (ESD) currents through the SCRs.

Abstract: A bipolar transistor device includes a substrate and at least one first transistor unit. The first transistor unit includes a first doped well of first conductivity type, at least one first fin-based structure and at least one second fin-based structure. The first fin-based structure includes a first gate strip and first doped fins arranged in the first doped well, and the first gate strip is floating. The second fin-based structure includes a second gate strip and second doped fins arranged in the first doped well, and the second gate strip is floating. The first doped fins, the second doped fins and the first doped well form first BJTs, and the first doped fins and the second doped fins are respectively coupled to high and low voltage terminals.

Abstract: A self-feedback control circuit is connected to a controller area network bus for controlling a high-level output and a low-level output, comprising a controller area network driving circuit and a replica circuit. The replica circuit is connected in parallel with the controller area network driving circuit and comprises an upper feedback path and a lower feedback path. The upper feedback path and the lower feedback path are connected jointly to a common mode, and the replica circuit provides a feedback signal from the common mode such that the feedback signal is able to be respectively transmitted to two individual transistors of the controller area network driving circuit through the upper feedback path and through the lower feedback path so as to control DC level stability of the high-level output and the low-level output.

Abstract: A slope control circuit is connected between a replica circuit and a controller area network bus. The replica circuit generates an upper and a lower feedback signal. The slope control circuit receives and is driven by the feedback signals for controlling a voltage slope of a high-level output and a low-level output. The slope control circuit comprises an upper and a lower driving circuit, individually connected between the replica circuit, the high-level output and the low-level output. The upper driving circuit and the lower driving circuit respectively include at least one charging and discharging circuit. By controlling the charging and discharging circuit, the present invention controls decreasing voltage slope of the high-level output to be symmetric to increasing voltage slope of the low-level output, and delay time of the circuit switching between different operating modes to be equivalent.

Abstract: A receiving circuit with an ultra-wide common-mode input voltage range applies to a controller area network (CAN) and comprises a resistor assembly electrically connected with a CANH and a CANL, a reference amplifier, a first input amplifier assembly, a second input amplifier assembly, and an analog adder. The receiving circuit receives voltages from the CANH and CANL. The resistor assembly bucks voltage, respectively generating CANH and CANL voltage divisions at first and second nodes and outputting the voltage divisions to the first and second input amplifier assemblies. The first and second input amplifier assemblies amplify the differential signal between the first and second nodes and convert the differential signal into single-end signals. The analog adder adds the single-end signals as the output signal. The receiving circuit can receive the signal ranging between the maximum and minimum common-mode voltages and reduce electromagnetic emission.

Abstract: A three-dimension (3D) integrated circuit (IC) package is disclosed. The 3D IC package has a package substrate having a surface. At least one integrated circuit (IC) chip with or without suppressing a transient voltage and at least one transient voltage suppressor (TVS) chip are arranged on the surface of the substrate and electrically connected with each other. The IC chip is independent from the TVS chip. The IC chip and the TVS chip stacked on each other are arranged on the package substrate. Alternatively, the IC chip and the TVS chip are together arranged on an interposer formed on the package substrate.

Abstract: A silicon-controlled rectification device with high efficiency is disclosed, which comprises a P-type region surrounding an N-type region. A first P-type heavily doped area is arranged in the N-type region and connected with a high-voltage terminal. A plurality of second N-type heavily doped areas is arranged in the N-type region. A plurality of second P-type heavily doped areas is closer to the second N-type heavily doped areas than the first N-type heavily doped area and arranged in the P-type region. At least one third N-type heavily doped area is arranged in the P-type region and connected with a low-voltage terminal. Alternatively or in combination, the second N-type heavily doped areas and the second P-type heavily doped areas are respectively arranged in the P-type region and the N-type region.

Abstract: The present invention discloses a serial transmission driving method, wherein a serial transmission driving device (STD) is connected with a first terminal (FT) and a second terminal (ST) of an equivalent load capacitor through a first differential bus (FDB) and a second differential bus (SDB). FDB and SDB are respectively connected with a high-potential terminal (HPT) and a low-potential terminal (LPT) through a first equivalent resistor and a second equivalent resistor. STD receives a trigger signal (TS) appearing during the transition between a turn-on signal (Ton) and a turn-off signal (Toff), generates a first potential (FP) and a second potential (SP) greater than FP according to TS, and respectively applies FP and SP to SDB and FDB. FP and SP fast change the potential of FT to be greater than that of ST. HPT and LPT maintain potentials of FDB and SDB until Toff ends.

Abstract: A method for fabricating a semiconductor-based planar micro-tube discharger structure is provided, including the steps of forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap, forming an insulating layer over the patterned electrodes and the separating block, and filling the insulating layer into the gap. At least two discharge paths are formed. The method can fabricate a plurality of discharge paths in a semiconductor structure, the structure having very high reliability and reusability.

Abstract: A silicon-controlled rectification device with high efficiency is disclosed, which comprises a P-type region surrounding an N-type region. A first P-type heavily doped area is arranged in the N-type region and connected with a high-voltage terminal. A plurality of second N-type heavily doped areas is arranged in the N-type region. A plurality of second P-type heavily doped areas is closer to the second N-type heavily doped areas than the first N-type heavily doped area and arranged in the P-type region. At least one third N-type heavily doped area is arranged in the P-type region and connected with a low-voltage terminal. Alternatively or in combination, the second N-type heavily doped areas and the second P-type heavily doped areas are respectively arranged in the P-type region and the N-type region.

Abstract: A low-cost ESD protection device for high-voltage open-drain pad is disclosed, which has a first high-voltage (HV) NMOSFET coupled to a high-voltage (HV) open drain pad, a ground pad, a HV block unit and an ESD clamp unit and a low-voltage (LV) bias unit coupled to the first HV NMOSFET, a low-voltage (LV) trigger, the ESD clamp unit and the ground pad. The LV trigger is coupled to the HV block unit. The HV block unit blocks a high voltage from the HV open drain pad diode during normal operation and generates a trigger signal to the LV trigger when an ESD event is applied to the HV open drain pad. Then, the LV trigger turns on the ESD clamp unit to discharge an ESD current and switches the LV bias unit to turn off the first HV NMOSFET.

Abstract: A high voltage open-drain electrostatic discharge (ESD) protection device is disclosed, which comprises a high-voltage n-channel metal oxide semiconductor field effect transistor (HV NMOSFET) coupled to a high-voltage pad and a low-voltage terminal and receiving a high voltage on the high-voltage pad to operate in normal operation. The high-voltage pad and the HV NMOSFET are further coupled to a high-voltage ESD unit blocking the high voltage, and receiving a positive ESD voltage on the high-voltage pad to bypass an ESD current when an ESD event is applied to the high-voltage pad. The high-voltage ESD unit and the low-voltage terminal are coupled to a power clamp unit, which receives the positive ESD voltage via the high-voltage ESD unit to bypass the ESD current.

Abstract: A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.

Abstract: A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation.

Abstract: A method for fabricating a semiconductor-based planar micro-tube discharger structure is provided, including the steps of forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap, forming an insulating layer over the patterned electrodes and the separating block., and filling the insulating layer into the gap. At least two discharge paths are formed. The method can fabricate a plurality of discharge paths in a semiconductor structure, the structure having very high reliability and reusability.

Abstract: A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region.

Abstract: A package structure and an electronic apparatus of the package structure are disclosed. The package structure includes a substrate and a plurality of pins. The plurality of pins is disposed on the substrate. The plurality of pins is interlaced to each other, so that a line along a specific direction will only pass one of the plurality of pins at most.

Abstract: The present invention is related to an improved power amplifier and a method for restraining power of the improved power amplifier. The improved power amplifier has an output power restraint unit, and the output power restraint unit is capable of restraining output power of the improved power amplifier when the output power is exceedingly large. A method for restraining power of a power amplifier, the method comprises the steps of: determining whether power of output powers signal are exceedingly large through a power signal transformation unit, if yes, adjusting two variable resistor of an input amplifier unit for adjusting the power of the power signals, and outputting the adjusted power signals for driving a load via output terminals of the power amplifier.