Abstract: A Class-D power amplifier having a distortion-suppressing function includes a gain control unit, a first PWM unit, a second PWM unit, a current control unit, and a level control unit. The level control unit includes at least one D flip-flop and at least one XNOR gate. The D flip-flop has an output end coupled with the gain control unit and an R end coupled with an output end of the XNOR gate. When the Class-D power amplifier has its positive output end and negative output end respectively and simultaneously outputting a high-level signal and a low-level signal to the XNOR gate, the XNOR gate outputs the high-level signal to the D flip-flop. Then the D flip-flop outputs the high-level signal to the gain control unit as feedback for controlling the gain control unit to reduce audio gain, thereby suppressing audio distortion.
Type:
Grant
Filed:
August 21, 2009
Date of Patent:
December 14, 2010
Assignee:
Amazing Microelectronic Corp.
Inventors:
Ming-Hsiung Chen, Shang-Shu Chung, Tung-Sheng Ku
Abstract: An ESD protection circuit suitable for applying in an integrated circuit with separated power domains is provided. The circuit includes a P-type MOSFET coupled between a first circuit in a first power domain and a second circuit in a second power domain. A source terminal of the P-type MOSFET is coupled to a connection node for connecting the first circuit and the second circuit. A gate terminal of the P-type MOSFET is coupled to a positive power line of the second power domain. A drain terminal of the P-type MOSFET is coupled to a negative power line of the second power domain. A body terminal of the P-type MOSFET is also coupled to the connection node.
Type:
Grant
Filed:
October 10, 2007
Date of Patent:
October 19, 2010
Assignee:
Amazing Microelectronics Corp.
Inventors:
Ming-Dou Ker, Yuan-Wen Hsiao, Ryan Hsin-Chin Jiang
Abstract: An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the negative power line and an input terminal of the triggering unit. The MOS capacitor is coupled between the positive power line and an input terminal of the triggering unit for ESD protection. During a normal power operation, a switching terminal of the triggering unit enables the MOS capacitor to be coupled between the negative power line and an input terminal of the triggering unit. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.
Type:
Grant
Filed:
August 5, 2009
Date of Patent:
October 19, 2010
Assignee:
Amazing Microelectronic Corp.
Inventors:
Ming-Dou Ker, Chin-Hao Chen, Ryan Hsin-Chin Jiang
Abstract: The present invention discloses a bidirectional PNPN silicon-controlled rectifier comprising: a p-type substrate; a N-type epitaxial layer; a P-type well and two N-type wells all formed inside the N-type epitaxial layer with the two N-type wells respectively arranged at two sides of the P-type well; a first semiconductor area, a second semiconductor area and a third semiconductor area all formed inside the P-type well and all coupled to an anode, wherein the second semiconductor area and the third semiconductor area are respectively arranged at two sides of the first semiconductor area, and wherein the first semiconductor area is of first conduction type, and the second semiconductor area and the third semiconductor area are of second conduction type; and two P-type doped areas respectively formed inside the N-type wells, wherein each P-type doped area has a fourth semiconductor area neighboring the P-type well and a fifth semiconductor area, and wherein both the fourth semiconductor area and the fifth semico
Type:
Grant
Filed:
March 20, 2008
Date of Patent:
August 31, 2010
Assignee:
Amazing Microelectronic Corp.
Inventors:
Wen-Yi Chen, Ryan Hsin-Chin Jiang, Ming-Dou Ker
Abstract: An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the positive power line and an input terminal of the triggering unit. The MOS capacitor has a first end and a second end. The first end is coupled to the input terminal of the triggering unit. During a normal power operation, a switching terminal of the triggering unit enables the second end of the MOS capacitor to be coupled with the positive power line. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.
Type:
Grant
Filed:
November 28, 2007
Date of Patent:
July 13, 2010
Assignee:
Amazing Microelectronic Corp.
Inventors:
Ming-Dou Ker, Chin-Hao Chen, Ryan Hsin-Chin Jiang
Abstract: An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.
Type:
Grant
Filed:
July 17, 2007
Date of Patent:
February 2, 2010
Assignee:
Amazing Microelectronic Corp.
Inventors:
Ming-Dou Ker, Yuan-Wen Hsiao, Ryan Hsin-Chin Jiang
Abstract: The present invention proposed a slew-rate control circuitry without the use of external components such as amplifiers. Therefore slew-rate control circuitry of the present invention not only provides an IC with build-in slew-rate control, but also reduces number of transistors used externally which will increase gate-oxide reliability of the IC. The slew-rate control circuitry of the present invention is primarily comprised by an output buffer and feedback circuitry, the output buffer mainly consisted four transistors and depends on output of the IC, these four transistors will interact with each other to control the slew-rate of IC output. Additional feedback circuitry and gate-tracking circuitry are also disclosed to enhance the performance of the slew-rate control circuitry.
Type:
Grant
Filed:
January 16, 2008
Date of Patent:
January 26, 2010
Assignee:
Amazing Microelectronic Corp.
Inventors:
Che-Hao Chuang, Tang-Kuei Tseng, Ryan Hsin-Chin Jiang
Abstract: A charge pump circuit with bipolar output comprises a first set of switch device capable of selectively connecting two terminals of a first transfer capacitor to a voltage source and a ground terminal, respectively, a second set of switch device capable of selectively connecting the two terminals of the first transfer capacitor to a grounded first storage capacitor and the voltage source, respectively, a third set of switch device capable of selectively connecting two terminals of a second transfer capacitor to the first transfer capacitor connected to the voltage source and the ground terminal, respectively, and a fourth set of switch device capable of selectively connecting the two terminals of the second transfer capacitor to a grounded second storage capacitor and the ground terminal, respectively.
Type:
Grant
Filed:
January 23, 2008
Date of Patent:
October 6, 2009
Assignee:
Amazing Microelectronic Corp.
Inventors:
Tang-Kuei Tseng, Juing-Yi Cheng, Ryan Hsin-Chin Jiang