Abstract: Abstract Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.
Abstract: Structures including crystalline material disposed in openings defined in a non-crystalline mask layer disposed over a substrate. A photovoltaic cell may be disposed above the crystalline material.
Type:
Application
Filed:
April 9, 2008
Publication date:
October 23, 2008
Applicant:
AmberWave Systems Corporation
Inventors:
Jizhong Li, Anthony J. Lochtefeld, Calvin Sheen, Zhiyuan Cheng
Abstract: Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on the semiconductor substrate while in situ doping the epitaxial layer to suppress facet formation. Suppression of faceting during selective epitaxial growth by in situ doping of the epitaxial layer at a predetermined level rather than by manipulating spacer composition and geometry alleviates the stringent requirements on the device design and increases tolerance to variability during the spacer fabrication.
Type:
Grant
Filed:
July 20, 2006
Date of Patent:
October 21, 2008
Assignee:
AmberWave Systems Corporation
Inventors:
Thomas A. Langdo, Anthony J. Lochtefeld
Abstract: A backside illuminated multi-junction solar cell module includes a substrate, multiple multi-junction solar cells, and a cell interconnection that provides a series connection between at least two of the multi-junction solar cells. The substrate may include a material that is substantially transparent to solar radiation. Each multi-junction solar cell includes a first active cell, grown over the substrate, for absorbing a first portion of the solar radiation for conversion into electrical energy and a second active cell, grown over the first active cell, for absorbing a second portion of the solar radiation for conversion into electrical energy. At least one of the first and second active cells includes a nitride.
Abstract: A method for forming a semiconductor structure, the method including forming in a processing chamber a dielectric layer over a substrate; and subsequently forming, in the same processing chamber and without removing the substrate therefrom, an electrode layer directly over and in contact with the dielectric layer.
Abstract: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.
Type:
Grant
Filed:
February 6, 2007
Date of Patent:
August 26, 2008
Assignee:
AmberWave Systems Corporation
Inventors:
Matthew T. Currie, Anthony J. Lochtefeld
Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
Type:
Grant
Filed:
October 15, 2004
Date of Patent:
August 12, 2008
Assignee:
AmberWave Systems Corporation
Inventors:
Mayank Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
Abstract: Structures including dielectric diffraction gratings. In some embodiments, laser devices include diffraction gratings defined by openings formed in a dielectric material.
Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
Type:
Grant
Filed:
September 23, 2004
Date of Patent:
August 5, 2008
Assignee:
AmberWave Systems Corporation
Inventors:
Mayank Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
Abstract: Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.
Abstract: Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free.
Type:
Application
Filed:
December 21, 2007
Publication date:
June 12, 2008
Applicant:
AmberWave Systems Corporation
Inventors:
Richard Westhoff, Christopher J. Vineis, Matthew T. Currie, Vicky K. Yang, Christopher W. Leitz
Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
Type:
Grant
Filed:
August 22, 2003
Date of Patent:
May 20, 2008
Assignee:
AmberWave Systems Corporation
Inventors:
Richard Westhoff, Vicky Yang, Matthew Currie, Christopher Vineis, Christopher Leitz
Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
Type:
Grant
Filed:
September 15, 2005
Date of Patent:
May 6, 2008
Assignee:
AmberWave Systems Corporation
Inventors:
Christopher Vineis, Vicky Yang, Matthew Currie, Richard Westhoff, Christopher Leitz
Abstract: Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.
Type:
Application
Filed:
September 7, 2007
Publication date:
May 1, 2008
Applicant:
AmberWave Systems Coporation
Inventors:
Jie Bai, Ji-Soo Park, Anthony Lochtefeld
Abstract: Some aspects for the invention include a method and a structure including a light-emitting device disposed over a second crystalline semiconductor material formed over a semiconductor substrate comprising a first crystalline material.
Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.