Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.
Abstract: Structures and methods for their formation include a substrate comprising a first semiconductor material, with a second semiconductor material disposed thereover, the first semiconductor material being lattice mismatched to the second semiconductor material. Defects are reduced by using an aspect ratio trapping approach.
Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance.
Abstract: Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free.
Type:
Grant
Filed:
January 27, 2004
Date of Patent:
February 19, 2008
Assignee:
AmberWave Systems Corporation
Inventors:
Richard Westhoff, Christopher J. Vineis, Matthew T. Currie, Vicky T. Yang, Christopher W. Leitz
Abstract: In forming an electronic device, a semiconductor layer is pre-doped and a dopant distribution anneal is performed prior to gate definition. Alternatively, the gate is formed from a metal. Subsequently formed shallow sources and drains, therefore, are not affected by the gate annealing step.
Type:
Grant
Filed:
May 18, 2006
Date of Patent:
February 5, 2008
Assignee:
AmberWave Systems Corporation
Inventors:
Anthony J. Lochtefeld, Matthew T. Currie
Abstract: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.
Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance.
Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
Type:
Application
Filed:
May 17, 2006
Publication date:
November 22, 2007
Applicant:
AmberWave Systems Corporation
Inventors:
Anthony J. Lochtefeld, Matthew T. Currie, Zhiyuan Cheng, James Fiorenza, Glyn Braithwaite, Thomas A. Langdo
Abstract: Methods for fabricating multi-layer semiconductor structures including strained material layers using a minimum number of process tools and under conditions optimized for each layer. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
Abstract: Methods of forming areas of alternative material on crystalline semiconductor substrates, and structures formed thereby. Such areas of alternative material are suitable for use as active areas in MOSFETs or other electronic or opto-electronic devices.
Type:
Application
Filed:
July 26, 2006
Publication date:
August 9, 2007
Applicant:
AmberWave Systems Corporation
Inventors:
Anthony Lochtefeld, Matthew Currie, Zhi-Yuan Cheng, James Fiorenza
Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
Abstract: A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer, and a Si1-yGey layer; removing the Si1-yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.
Type:
Grant
Filed:
December 16, 2004
Date of Patent:
May 15, 2007
Assignee:
AmberWave Systems Corporation
Inventors:
Eugene A. Fitzgerald, Richard Hammond, Matthew Currie
Abstract: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.
Type:
Grant
Filed:
May 19, 2005
Date of Patent:
April 24, 2007
Assignee:
AmberWave Systems Corporation
Inventors:
Matthew T. Currie, Anthony J. Lochtefeld
Abstract: A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1?xGex layer on a substrate, a strained channel layer on the relaxed Si1?xGex layer, and a Si1?yGey layer; removing the Si1?yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.
Type:
Application
Filed:
September 13, 2006
Publication date:
April 12, 2007
Applicant:
AmberWave System Corporation
Inventors:
Eugene Fitzgerald, Richard Hammond, Matthew Currie
Abstract: Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.
Type:
Grant
Filed:
March 9, 2006
Date of Patent:
April 10, 2007
Assignee:
AmberWave Systems Corporation
Inventors:
Matthew T. Currie, Anthony J. Lochtefeld
Abstract: Monolithic lattice-mismatched semiconductor heterostructures are fabricated by bonding patterned substrates with alternative active-area materials formed thereon to a rigid dielectric platform and then removing the highly-defective interface areas along with the underlying substrates to produce alternative active-area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations.
Type:
Application
Filed:
September 7, 2005
Publication date:
March 8, 2007
Applicant:
AmberWave Systems Corporation
Inventors:
Matthew Currie, Anthony Lochtefeld, Zhiyuan Cheng, Thomas Langdo