Abstract: A spread-spectrum modulation method and circuit for a clock generator phase-locked loop (PLL). A dither signal is injected into a PLL in synchronization with and having the same period or fraction of the same period as the phase comparison performed within the PLL. Over such period, the phase error caused by the modulation will integrate to zero and hence avoid transmitting a disturbance to the loop. A particular embodiment utilizes an output of the reference divider and/or feedback divider within the PLL to generate the dither signal. Such a configuration avoids the need for additional hardware which otherwise would increase the chip area and/or cost of the device. The reference divider and/or feedback divider is made up preferably of a linear feedback shift register (LFSR). One or more stages of the LFSR provide an output which is used to generate the dither signal. In a preferred embodiment, the output from the LFSR exhibits a pseudo-random sequence.

Abstract: Characterization of plasma-induced damage in semiconductor manufacturing has long been considered unimportant because the damage had no discernable effect on circuit performance. With increasing transistor counts on an integrated circuit, the damage-induced parasitics are becoming increasingly important. Electrical characterization of such effects provides a far more sensitive method for determining the extent of damage and the effectiveness of efforts to repair the damage. A measurement of diode leakage current through a plasma-etch effect test diode which is formed completely within an active device region, removed from field oxide regions quantifies the extent of damage created by a plasma and the effectiveness of a repair technique that may be applied to the process.

Abstract: Characterization of plasma-induced damage in semiconductor manufacturing has long been considered unimportant because the damage had no discernible effect on circuit performance. With increasing transistor counts on an integrated circuit, the damage-induced parasitics are becoming increasingly important. Electrical characterization of such effects provides a far more sensitive method for determining the extent of damage and the effectiveness of efforts to repair the damage. A measurement of diode leakage current through a plasma-etch effect test diode which is formed completely within an active device region, removed from field oxide regions quantifies the extent of damage created by a plasma and the effectiveness of a repair technique that may be applied to the process.

Abstract: A wordline driver for a semiconductor memory array having a circuit for selecting and deselecting the first end of an addressed wordline and a circuit for deselecting the second end of the addressed wordline. The first and second ends of the addressed wordline are deselected at substantially the same time. The first end of the wordline is selected and deselected responsive to a strobe waveform and the second end of the wordline is deselected responsive to an RL Strobe waveform. The RL Strobe waveform is derived from a delayed strobe waveform.

Abstract: An input buffer capable of operating at a first power supply voltage level or a second power supply voltage level with the operating voltage level selectable during manufacture. At least one shortable transistor is disposed between the power supply voltage input and a buffer circuit which is connected between an input and an output of the buffer circuit. When the first voltage is the intended operating voltage the at least one shortable transistor is shorted. The first operating voltage level meets the requirements of a CMOS device and the second operating voltage level meets the requirements of a TTL device. The shortable transistor can be either a p-channel or an n-channel transistor and the short can be done by a metal layer short, a polysilicon short, a depletion implant, or with vias during manufacture.

Abstract: A read only memory (ROM) array is disclosed which includes a) a voltage supply providing an operating voltage level, b) a plurality of word-lines, c) a multiplicity of ROM transistors, and d) a word-line clamper. The ROM transistors are divided into turned on and turned off transistors. Each ROM transistor has a gate connected to one of the word-lines, a gate oxide beneath the gate, whose thickness is less than 250 .ANG., and a channel beneath the gate oxide. The turned off transistors additionally have a ROM implant in their channel whose dosage is no larger than the amount which generates a predetermined desired minimal band-to-band tunneling current The ROM implant and gate oxide thickness define a threshold voltage for the tamed off tranistors, the threshold voltage being less than the operating voltage level. The word-line damper provides a word-line voltage to each of the word-lines, the word-line voltage being clamped to a voltage level no higher than the threshold voltage of the turned off transistor.

Abstract: A method of manufacturing a ROM array to minimize band-to-band tunneling is described. The method includes the steps of: a) implanting bit lines into the core area of a substrate as per a later-removed bit line mask, b) providing a ROM oxide layer over the entirety of the substrate, c) etching the ROM oxide layer only from the periphery area as per a later-removed core protect mask, d) providing a gate oxide layer over the entirety of the ROM array, e) laying down polysilicon rows in the core area as per a polysilicon mask and f) implanting a ROM implant into selected areas of the core area, thereby to produce turned off core transistors. The thickness of the gate oxide layer and the ROM oxide layer are independent of each other.

Abstract: A clock delay circuit for generating a delay for a sense amplifier release signal in an integrated circuit semiconductor memory device is disclosed. Rather than utilize traditional programmable capacitors that must be trimmed on a die by die basis, the novel clock delay circuit disclosed utilizes a small ROM, EPROM, EEPROM or FLASH array coupled to a bit line emulator to provide a clock delay matched to the larger main array. The size of the small memory array is on the order of 5 to 10 bit lines by 5 to 10 word lines. One cell within the small array is fixed to be continuously selected. The selected cell is coupled to the clock delay node along with the bit line emulator. The bit line emulator models the capacitance of the actual bit line used in the main array. However, the circuit is constructed so that a much larger signal is generated by the delay circuit such that sense amplifiers detect the correct signal.

Abstract: A multiple stage tracking filter includes a self-calibrating RC oscillator, a resistor connected to the self-calibrating RC oscillator and a capacitor connected to the self-calibrating RC oscillator. The filter further includes a switched capacitor filter element connected to the self-calibrating RC oscillator. The switched capacitor filter elements include a switch which is controlled by a timing signal from the self-calibrating RC oscillator. A method of filtering a signal includes the steps of operating a self-calibrating RC oscillator to generate a timing signal, tuning a plurality of cascaded filter elements with the generated timing signal and passing a signal through the plurality of tuned cascaded filter elements.

Abstract: A timer initialization circuit is used to stabilize a timing signal of a system timed using a core oscillator. The timer initialization circuit includes a circuit which disables the core oscillator during a power-down mode and re-enables the core oscillator upon termination of the power-down mode. The timer initialization circuit also includes a circuit which stores an indication of an oscillation frequency at which the circuit operates immediately preceding the power-down mode.

Abstract: An RC oscillator includes an RC network for forming a time constant equal to the RC product. However, this RC time constant is not used in the manner of a typical RC network to set the frequency of oscillation. Instead, the RC oscillator disclosed herein includes a separate oscillator, such as a voltage-controlled oscillator (VCO), and uses the RC time constant to compare with the oscillator-generated period and to adjust the frequency of the overall RC oscillator circuit in accordance with the comparison. The RC oscillator is self-calibrating.

Abstract: A component detector circuit operates to detect the presence or absence of a circuit component, such as an external component. A resistor detecting circuit includes a biasing circuit connected to the resistor. The biasing circuit generating a bias current. The resistor detecting circuit also includes a bias current threshold detector connected to the biasing circuit and a circuit connected to the bias current threshold detector which generates a signal indicative that the bias current is lower than threshold. A capacitor detecting circuit includes a circuit connected to a resistor and configured to be connected to a capacitor which establishes a time constant proportional to an RC product of the resistor and capacitor.

Abstract: A low power RC oscillator includes a low power bias circuit and an RC network. The RC network is used to form a time constant equal to the RC product. However, this RC time constant is not used in the manner of a typical RC network to set the frequency of oscillation. Instead, the RC oscillator disclosed herein includes a separate oscillator, such as a voltage-controlled oscillator (VCO), and uses the RC time constant to compare with the oscillator-generated period and to adjust the frequency of the overall RC oscillator circuit in accordance with the comparison. The RC oscillator is self-calibrating.

Abstract: A digitally-tuned oscillator (DTO) includes a digital-to-analog converter (DAC) and an RC oscillator. The RC oscillator includes an RC circuit for forming a time constant equal to the RC product. However, this RC time constant is not used in the manner of a typical RC network to set the frequency of oscillation. Instead, the RC oscillator disclosed herein includes a separate oscillator, such as a voltage-controlled oscillator (VCO), and uses the RC time constant to compare with the oscillator-generated period and to adjust the frequency of the overall RC oscillator circuit in accordance with the comparison. The RC oscillator is self-calibrating.

Abstract: A monolithic frequency converter using a feedback control loop generates a source of synthesized frequency signals over a wide dynamic range based on a timing source such as a crystal oscillator or an external frequency source. The frequency converter includes a controlled oscillator, a frequency counter, a timing signal generator and, connected between the frequency counter and the controlled oscillator, a digital to analog converter and a difference integrator. The controlled oscillator generates a clock signal at a frequency controlled by an electrical signal. The difference integrator is connected to an input signal terminal and connected to the timing signal generator. The difference integrator determines a difference signal between the input signal and a signal operated upon by the digital to analog converter and integrates the difference signal under control of a timing signal generated by the timing signal generator.

Abstract: An asynchronous digital arbiter circuit suitable for use in computer systems applications requiring fast asynchronous arbitration between two asynchronous inputs. The arbiter resolves which of two input signals is to be granted access, and provides a busy signal to the source of the other input signal. The arbiter consists solely of standard digital logic circuit elements including logic gates, flip-flops, and inverters.

Abstract: An electronic filter which has particular application for use as an antialiasing filter in sampled data systems fabricated so as to utilize high resistivity diffused regions (36, 37) within the semiconductor body (31), as opposed to low resistivity polycrystalline silicon resistors. Furthermore, the values of the resistors and capacitors selected for use in a filter constructed in accordance with this invention are such that the high resistivity resistors require a small amount of space, and are physically located beneath the capacitors (33, 34, 35) used in the filter of this invention. The lower plate (33) of the capacitor is connected to a fixed voltage potential, thereby in effect shielding the underlying resistors from the deleterious effect of changes in voltage, and thus preventing the modulation of the resistance values of the resistors.

Abstract: A circuit (8) is provided for driving the segment and back plane of a liquid crystal display. The circuit includes a plurality of transistors (Q1 to Q10) connected such that the base emitter junctions of the transistors are coupled in series between a voltage source and ground. The voltage at the emitter one of the transistors (Q3) is used to provide a first voltage (VLOW) for driving the LCD and a voltage at the emitter one of the other transistors (Q10) is used to provide the other voltage (VHIGH) for driving the LCD. Of importance, because the difference between the first and second voltages depends upon the voltage drop across a set of PN junctions, this difference in voltage varies with temperature. Specifically, the difference in voltage increases at low temperatures and decreases at high temperatures. In this way, the voltage used to drive the LCD is automatically compensated for temperature variations.

Abstract: A programmable logic array 100 which uses parallel transistor logic gates 150 arranged in a compact layout for fast signal propagation. One of logic planes 120 or 130 is prechargeable to substantially reduce power consumption using a simple, one-phase clock.

Abstract: An oxide fuse, and method of forming same, formed by a thin layer of oxide dielectric between a lower electrode substrate and an upper electrode. A fuse-programming bias of approximately 15V causes Fowler-Nordheim tunneling at low temperature to damage the dielectric layer, and shorts the upper and lower electrodes together. The oxide layer is advantageously formed simultaneously with the gate oxide layer in an EEPROM.