Abstract: A novel switched capacitor gain stage uses a unique circuit design and clocking technique that reduces the component mismatch offset voltage and the clock-induced feedthrough offset voltage produced by the circuit. The total capacitance ratio between the input capacitors and the feedback capacitor necessary to achieve a desired total gain is also minimized.

Abstract: PASS transistors are used to reduce the layout complexity of logic circuits by using PASS transistors connected to pass a first and second input function to an output node in response to selected CONTROL signals, thereby to generate a selected output function on the output node. The PASS transistor comprises a transistor capable of passing an input function in response to a CONTROL signal applied to the transistor thereby to generate an output function related to the input function. In general, the input function comprises less than all of a set of input variables and the CONTROL function comprises one or more of the remainder of the set of input variables.

Abstract: An operational amplifier has one noninverting input lead (116), and two inverting input leads (117a, 117b). One of these inverting input leads (117a) is utilized to compensate for the effects of the inherent offset voltage (V.sub.off) of the operational amplifier, and the second inverting input lead (117b) receives an input signal to be amplified or compared.

Abstract: A unique CVSD CODEC is provided utilizing switched capacitor technology. This CVSD CODEC includes a syllabic filter which provides one of a large number of possible step sizes, thereby allowing the CVSD CODEC to accurately track and convert a wide range of input voltages. The CVSD CODEC includes coincidence logic, which determines how accurately the input voltage is being tracked, and a syllabic filter which provides an appropriate step size based upon the output signals of the coincidence logic. Large step sizes are provided for converting input voltages having large magnitudes, and small step sizes are used to convert input voltages having small magnitudes, thereby providing the very accurate resolution of input voltages over the wide range of magnitudes, while minimizing the bit rate required.

Abstract: A differential operational amplifier is provided with a feedback loop which continuously adjusts the common mode voltage level of the amplifier so that it lies in the center of the dynamic range of the amplifier. The feedback loop measures the instantaneous common mode voltage level and compares it with a reference voltage which is set to reflect the desired common mode voltage. An error signal is generated and fed back into the amplifier to adjust the instantaneous common mode voltage level towards the reference level. Frequency compensation is also provided to overcome the phase shift introduced by the use of RC networks.

Abstract: A CMOS push-pull output buffer (171) is constructed utilizing a plurality of N channel transistors (74, 75, 76) and a plurality of P channel transistors (71, 72, 73) connected in series. The voltages applied to the gates of the N channel transistors and P channel transistors are selected to divide the high voltage (+V) substantially equally across the P channel transistors, when the P channel transistors are turned off, and substantially evenly divide the high voltage across the N channel transistors, when the N channel transistors are turned off.In another embodiment of this invention, selected ones of the N channel and P channel transistors are formed in order to have a high drain to bulk breakdown voltage.In another embodiment of this invention, a plurality of N channel and a plurality of P channel transistors are connected in series and driven by a single ended control voltage (C.sub.

Abstract: A programmable transversal filter utilizes a plurality of programmable multiplying means. The result of each multiplication is summed by a summing circuit, thus providing an output signal. The delay network comprises a plurality of signal sample and hold circuits which are selectively connected to the input bus in sequence, in order that one sample and hold circuit may store an analog signal sampled during the present time instant, with other sample and hold circuits storing a plurality of analog signals each of which has been sampled during a corresponding one of a plurality of preceding sample periods. The filter also includes a plurality of reference sample and hold circuits which store error voltages equal to the error voltage component of the voltages provided by the signal sample and hold circuits.A first analog cross-point switch is utilized wherein each of said plurality of time delayed analog signals may be selectively applied to a selected multiplying means.

Abstract: A programmable transversal filter (10) utilizes a plurality of programmable multiplying means (M.sub.1 -M.sub.4). The result of each multiplication is summed by a summing circuit (7), thus providing an output signal (y(t)). The delay network of this invention comprises a plurality of sample and hold circuits (S.sub.1 -S.sub.4) which are selectively connected to the input bus in sequence, in order that one sample and hold circuit may store an analog signal sampled during the present time instant, with other sample and hold circuits storing a plurality of analog signals each of which has been sampled during a corresponding one of a plurality of preceding sample periods.An analog cross-point switch (51) is utilized wherein each of said plurality of time delayed analog signals may be selectively applied to a selected multiplying means.

Abstract: A switched capacitor filter is designed utilizing two switched capacitor charge pumps connected in series. These two charge pumps operate with different clock frequencies thereby allowing charging of a storage capacitor at a higher frequency, thereby decreasing incremental voltage steps during the charging of the storage capacitor, resulting in the generation of a smoother exponential voltage rise.

Abstract: A method for fabricating an integrated circuit semiconductor device comprised of an array of MOSFET elements having self-aligned or self-registered connections with conductive interconnect lines. The method involves the formation on a substrate of a thick oxide insulation layer (30) surrounding openings (99) therein for the MOSFET elements. A gate electrode (38) within each opening is utilized to provide self-registered source (42) and drain (44) regions and is covered on all sides and on its top surface with a gate dielectric layer (46). After the formation of the source-drain regions a relatively thin dielectric protective layer (38) is applied to the entire chip prior to the application of an upper insulative layer (50).

Abstract: Capacitors or dual layer metalization interconnects are formed in an integrated circuit utilizing two layers of polycrystalline silicon (22, 24) separated by a thin insulation region (23). The insulation region formed between the two polycrystalline silicon regions has substantially fewer defects than the insulation regions used in prior art techniques due to the use of a unique process wherein the polycrystalline silicon layer (24) overlying the insulation layer (23) protects the insulation layer from attack during subsequent processing. An improved dielectric strength is provided by forming the insulation region (23) utilizing composite layers of silicon oxide (23a, 23c) and silicon nitride (23b).

Abstract: An electronic comparator circuit (10) adapted for implementation as an integrated circuit semiconductor device provides high resolution and high speed performance. The circuit comprises a first differential amplifier (12) with clamping diodes (50, 52) that allow a fast response; a source-follower stage (14) connected to the first differential amplifier for buffering its output to enable it to be broadbanded; a second differential amplifier (16) driven by the source-follower stage for handling large signal swings while providing additional gain, a level shift stage (18) for driving the output stage in a class A-B mode, and a cascode output stage (20) which provides increased circuit gain and an output signal which ranges from the positive supply voltage (V.sub.DD) to the negative supply voltage (V.sub.SS).

Abstract: An AGC circuit (12) contains a programmable gain stage comprising an operational amplifier (150) and one or more capacitor arrays (101, 121) for controlling the closed loop gain of the operational amplifier. The output signal (V.sub.O) of this operational amplifier is rectified, and the rectified signal is alternately integrated with a reference voltage (V.sub.ref) of opposite polarity to the rectified AGC signal. The polarity of the integrated voltages operates a counter stage (200). The output bits (0.sub.2 -0.sub.N) of the counter are used to control switches (134-2 through 134-N, 135-2 through 135-N, 110-2 through 110-N, 111-2 through 111-N) in the one or more capacitor arrays which control the closed loop gain of the operational amplifier of the AGC circuit of this invention.

Abstract: This invention provides a uniquely designed switched capacitor multiplier/adder (129) which also functions as a digital-to-analog converter in a single subcircuit. The multiplier/adder, in a single operation, multiplies an analog voltage by a binary coefficient, and sums this product with a second analog voltage. The use of this unique subcircuit results in a significant reduction in space requirements for the construction of, for example, a speech synthesis circuit utilizing linear predictive coding over prior art circuits. This reduction in size results in a significant reduction in the manufacturing costs for this circuit over prior art circuits, and additionally allows the option of including on the speech synthesis chip a memory for the storage of binary representations of to-be-synthesized speech patterns.

Abstract: A semiconductor READ ONLY MEMORY (ROM) device is constructed by using a series of word lines as a mask during the fabrication of the underlying bit lines. The width of the word lines over each memory cell determines the characteristics of that cell (i.e. programmed or unprogrammed).

Abstract: An operational amplifier gain stage utilizing switched capacitor resistor equivalent circuits is designed utilizing a delayed clock reference signal (.phi..sub.D, .phi..sub.D) in a unique manner, thereby eliminating the effects of spurious error voltages (E.sub.S) generated when utilizing metal oxide silicon field effect transistors as switches (12, 15, 21, 23, 25). The single remaining MOSFET switch (21) which will contribute a spurious voltage component to the output of the operational amplifier gain stage is designed in such a manner as to minimize the spurious voltage generated during operation of the MOSFET switch. A single dummy switch (31) is utilized to further minimize the spurious voltage generated by this single MOSFET switch.

Abstract: An integrator circuit utilizing an operational amplifier (19) and switched capacitor elements (11, 13 and 16) in place of resistors in such a manner as to provide compensation for voltage offsets present in the operational amplifier resulting in an output voltage (V.sub.OUT) free from the effects of voltage offsets inherent in operational amplifiers.

Abstract: In an analog to digital converter circuit for a CODEC a single reference voltage is used for comparing both positive and negative input signals. The circuit comprises a capacitor array to define the decision levels corresponding to the end points of companding elements with the top plates of all capacitors in the array being connected in parallel through a single switch from an incoming analog signal source and to one input of a comparator. The bottom plate of each capacitor is connected to one of a series of three-way switches, all of which have separate terminals connected to the output of a voltage reference, to separate switches on a linear resistor string connected to the voltage reference output, and to ground. All switches are controlled by control logic connected to the comparator output.

Abstract: An integrated circuit digital to analog converter comprised of MOS current mirrors and utilizing additional MOS devices to provide transmission gates and control means. Each transmission gate 36 is connected to a source of digital data to be converted and the mirroring device for each transmission gate 36 has a channel width with some predetermined proportional relationship to the channels of input transistors 12 and mirroring output MOS transistors 14 to 44 with the input transistor 12 connected to a constant current source, the total output mirroring current of the output mirroring transistors is in quantized analog form and varies according to the cumulative currents from the mirroring MOS transistors as the transistors are activated. The invention may be embodied in linear multiplying, non-linear and companding converters.

Abstract: In the present invention, analog voice information is sampled at a first sampling rate, during periods when voice information is to be transmitted at a frequency which provides a digitized voice rate equal to the transmission rate capability of the transmission channel. During periods when both voice and data are to be transmitted, the analog voice information is sampled at a second sampling rate less than the first sampling rate, thus allowing the merged voice and data information to have a total digitized transmission rate equal to the transmission rate capability of the transmission channel.