Abstract: A semiconductor memory device is provided comprised of an integrated array of cells formed on a substrate in conjunction with parallel spaced-apart bit lines and conductive word lines that are perpendicular to the bit lines. A plurality of V-shaped recesses are located between and extend perpendicular to adjacent parallel bit lines. Two cells share each recess and each cell includes a VMOS transistor formed by one end portion of the recess and an isolated buried source region located under the adjacent bit line. A channel stop region is located between and isolates the VMOS transistors and their respective buried source regions at opposite ends of each recess. Thus, the VMOS pass gate is shared between adjacent bit lines and bit line capacitance is minimized. Also, the VMOS pass gates are self-aligned to eliminate alignment tolerances and minimize bit line capacitance. The invention also includes an efficient method for producing a semiconductor memory device with such an array of cells.

Abstract: Extremely cold gaseous nitrogen is used as a cooling medium in the highly exothermic reaction between a chemical etch solution and silicon. This greatly increases the throughput of silicon material through the etchant over prior art techniques, particularly where it is desired to maintain the temperature of the etchant solution below 25.degree. C.

Abstract: An integrator circuit utilizing an operational amplifier and switched capacitor elements in place of resistors in such a manner as to provide compensation for voltage offsets present in the operational amplifier resulting in an output voltage free from the effects of voltage offsets inherent in operational amplifiers.

Abstract: An autozero loop for eliminating offsets in the analog to digital converter section of a voice frequency coder-decoder (CODEC) utilizing an array of capacitors and a linear resistor string. The autozero loop functions with a relatively small time constant to null offsets quickly during the power-up phase of CODEC operation and with a higher time constant after the power-up phase. A dual bandwidth sub-circuit in the loop is connected to a voltage generator and controlled by signals from a logic circuit to operate at different bandwidths and thus provide different offset cancelling feedback signals during the power-up and normal operating phases.

Abstract: A switched capacitor filter is designed utilizing two parallel switched capacitor charge pumps. These two, parallel charge pumps operate out of phase with each other, thereby allowing charging of a storage capacitor at a rate equal to twice the clock frequency, thereby decreasing incremental voltage steps during the charging of the storage capacitor.

Abstract: An operational amplifier (10a) comprised of MOSFET elements is disclosed which provides for a variable drive for an output stage that results in lower power dissipation and increased gain factor over comparable circuits using constant bias drive for the output stage. A bias section (14) comprised of complementary MOS elements (24, 26) is connected to a single MOSFET (40) that furnishes constant current to the signal input section of a differential amplifier section (20). The output of this differential amplifier is furnished by one path (70) directly to one complementary MOSFET element (72) of an output stage (18) and by another path (114) to a level shift section (16) which provides an output to a second complementary MOSFET element (80) of the output stage. Thus, the circuit functions under class A-B operation at low power dissipation and provides high open loop gain.

Abstract: An interpolation or smoothing filter circuit for a switched-capacitor system which transforms the sampled-and-held output signals from a switched-capacitor filter into sampled-and-held signals with a doubled sample rate. The circuit comprises an operational amplifier whose noninverting input lead is connected to a switched capacitor network which receives the sampled-and-held input signals at the normal sample rate. The network includes two separate capacitors controlled by switches operable at two alternating clock phases and connected to provide the desired summation and holding of charges. Feedback leads connected between the amplifier output lead and its noninverting input lead and containing additional capacitors cooperate with the input network to produce an output signal that is sampled-and-held at twice the sample rate of the input signal.

Abstract: A switched-capacitor cosine filter for a sampled-data system functions to reject extraneous frequency components of an incoming analog signal around the sampling frequency, thereby avoiding aliasing. The filter comprises an operational amplifier whose inverting input receives input signals through a switched input capacitor controlled by a four-switch network controlled by alternating clock phases and feedback signals from the amplifier output through a feedback capacitor. The transfer function of the circuit provides a zero of transmission at the sampling frequency, thereby eliminating unwanted frequency components. A self-contained version of the cosine filter is provided by the addition of another grounded switched capacitor with appropriately timed switches in the feedback network.

Abstract: An operational amplifier is designed to eliminate the effects of inherent voltage affects when used as a voltage comparator, while maintaining a high slew rate and a fast response time by providing a feedback capacitor which can be connected and disconnected between the output terminal and the noninverting current mirror input leg.

Abstract: An operational amplifier circuit comprised of complementary MOS transistors and having a bias section, a differential amplifier section, a level shift stage and an output stage, provides for frequency compensation using two capacitors. One capacitor, connected between the differential amplifier section and the output stage through a CMOS transmission gate that functions as a resistor, acts as the dominant pole of the transfer function. A second capacitor between the amplifier section output node and a level shift transistor, functions to remove the secondary poles in the transfer function and cause the dominant pole to occur at a higher frequency.

Abstract: A method for fabricating a complementary metal-oxide-silicon (CMOS) integrated circuit device by forming a composite layer of oxide and nitride on the surface of a silicon substrate defined into predetermined areas for the subsequent formation of transistors, masking the substrate to expose preselected areas for P-wells, ion implanting P-type material in the exposed areas to form P-wells so that a relatively high doping level is provided to a greater depth around composite areas within the P-wells areas and a relatively lower doping level is established under the composite layer areas with the P-wells. The ion implantation of P-type material may be accomplished in either a single stage or a two stage procedure.

Abstract: An elliptic state variable filter uses switched capacitors controlled by an arrangement of switches that provides for a frequency response independent of stray capacitors in the circuit. The filter section comprises three integrating operational amplifiers connected in series, with a feedback connection between the output of the second operational amplifier and the circuit input to the first operational amplifier. Signals via a feed forward connection from the circuit input and the outputs of the first and second operational amplifier are summed by the third operational amplifier. Transmission zeros of the filter transfer function are realized independent of poles and with a feed forward arrangement which places them inherently on the unit circle and produces infinite loss at each zero frequency despite variations in capacitor ratios in the circuit.

Abstract: An operational amplifier of MOSFET elements is disclosed which provides for a variable drive for an output stage that results in lower power dissipation and increased gain factor over comparable circuits using constant bias drive for the output stage. A bias section comprised of complementary MOS elements is connected to a single MOSFET that furnishes constant current to the signal input section of a differential amplifier section. The output of this differential amplifier is furnished by one path directly to one complementary MOSFET element of a high impedance output stage and by another path to a level shift section which provides an output to a second complementary MOSFET element of the output stage. Thus, the circuit functions under class A-B operation at low power dissipation and provides high open loop gain. Additional embodiments of the invention utilize three MOSFET elements in the level shift section or an additional output stage having an NPN transistor in combination with an N-channel MOSFET.

Abstract: A semiconductor memory device is provided comprised of an integrated array of cells formed on a substrate in conjunction with parallel spaced-apart bit lines and conductive word lines that are perpendicular to the bit lines. A plurality of V-shaped recesses are located between and extend perpendicular to adjacent parallel bit lines. Two cells share each recess and each cell includes a VMOS transistor formed by one end portion of the recess and an isolated buried source region located under the adjacent bit line. A channel stop region is located between and isolates the VMOS transistors and their respective buried source regions at opposite ends of each recess. Thus, the VMOS pass gate is shared between adjacent bit lines and bit line capacitance is minimized. Also, the VMOS pass gates are self-aligned to eliminate alignment tolerances and minimize bit line capacitance. The invention also includes an efficient method for producing a semiconductor memory device with such an array of cells.

Abstract: For an integrated circuit semiconductor device having a multiplicity of MOSFET elements, voltage-invariant capacitors, each with metal as one plate and either polysilicon or source-drain diffusion as the second plate, are created by regrowing a thin oxide layer to provide the dielectric of the capacitor during the normal MOSFET processing sequence.

Abstract: A round off correction logic circuit is disclosed for inclusion within a floating point arithmetic binary digital multiplier implementing a modified Booth's algorithm for generating a final product of binary digits. The round off logic circuitry is connected in the multiplier for rounding its final product off to a predetermined binary digit without requiring the multiplier to generate any of the less significant binary digits to the right of the predetermined binary digit. Multiplier circuitry otherwise required to generate an unrounded final product prior to round off is eliminated without loss of accuracy in round off.

Abstract: A semiconductor programmable read only memory device (PROM) utilizes an array of memory cells each having an area basically defined by the intersection of a bit line and a word address line. On a substrate of one conductivity type is an upper layer of material of the opposite conductivity within which are diffused bit lines of the same conductivity material as the substrate. The crossing address lines are conductive material formed on an insulating layer that covers the diffused bit lines and the upper layer. Each cell is a single transistor element in the form of a V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of threshold logic. Each MOSFET is formed by a V-shaped recess at the intersection of each bit line and address line that extends through the diffused bit line, (which serves as the transistor drain) and into the substrate (which serves as the source and ground plane of the device).

Abstract: A semiconductor memory core structure comprised of an array of cells each having a single IGFET device formed in a recess located on one side of a diffused bit line and directly above a buried storage capacitor. The diffused bit line forms one source or drain region while the buried storage capacitor forms the other source and drain region. With the channel and gate between the two source and drain regions located on only one sidewall of the recess, the gate to drain and bit line capacitance is reduced, thereby providing increased signal power and a higher signal level to a sense amplifier than heretofore available.

Abstract: A high-pass switched capacitor biquadratic filter based on the bilinear z-transform. The filter comprises first and second integrating operational amplifiers connected in series and in combination with a third operational amplifier that serves as a sample and hold and also generates one simple pole and zero pair in the circuit transfer function thereby enabling the circuit to provide for a high degree of filter efficiency in a preselected frequency range. The operational amplifiers are connected to and operate in cooperation with capacitors of a predetermined size which are switched on and off continuously by two phase clock signals supplied to the circuit. The loss characteristic of the filter can be programmed by varying the clocking frequency. Higher order filters can be obtained by the tandem connection of second order circuit sections followed by one or more first order pole-zero section.

Abstract: A switched capacitor sampled data elliptic filter for data transmission or communication systems is disclosed. The filter section comprises three integrating operational amplifiers connected in series with a negative feedback connection between the output of the second operational amplifier and the input to the first operational amplifier, which is also connected to the input voltage source. Signals via a feed forward connection from the input voltage source and the outputs of the first and second operational amplifiers are summed by the third operational amplifier. Switched capacitors in the feed forward connection, the negative feedback connection, the inputs to all three operational amplifiers and in feedback sections of the first and third operational amplifiers are all connected to a two-phase clock driver operated at a preselected frequency.