Abstract: An oscillation circuit including a resonating element such as a crystal, an inverting amplifier and a resistor that each span the resonating element terminals, and two capacitors that capacitively couple the resonating element terminals to ground. An AC current source such as a temperature compensated and properly trimmed ring oscillator generates a differential AC current when active. The differential AC current has a frequency that is within a tolerance of the resonant frequency of the resonant element for a given set of operating conditions. Two buffers connect the differential outputs of the AC current source to respective terminals of the resonating element to thereby shorten startup time. A control logic circuit carefully times the application of the differential AC current to the resonating element terminals such that the current is applied for a sufficient time such that startup would occur under any anticipated operating condition.

Abstract: An SRAM memory includes a pull-up device coupled to each row of word lines in an array of SRAM cells. The pull-up devices are sized such that when a row is selected, the time for the associated word line to fully charge is sufficiently slow such that data stored in the selected SRAM cells are not corrupted during a read operation. By slowly charging the word lines, the corresponding access transistors are also slowly turned on, resulting in the coupled bit lines slowly charging or discharging from the data stored in the SRAM cell. Because there is not a sudden large charge transfer between the stored data and the coupled bit line, the data will not be corrupted during a read operation, and read precharge circuitry is not required.

Abstract: A fabricated multiple layer integrated circuit in which adequate planarization is accomplished using irregularly shaped and properly spaced conductive filler features that are spaced in such a way that capacitive coupling of the conductive filler features with the active conductive regions is reduced. The overall layout area of the conductive filler features is reduced to thereby reduced capacitive coupling with active conductive above and below. In addition, a relatively small edge of the feature is closest to the active conductive in the same conductive layer thereby further reducing capacitive coupling.

Abstract: A programmable voltage reference circuit that includes a current-to-voltage converter circuit, a voltage-to-current converter circuit, and a floating gate. The current-to-voltage converter circuit has two current input terminals and a voltage output terminal. The voltage-to-current converter circuit has two voltage input terminals and two current output terminals. The two current output terminals are each coupled to a corresponding current input terminal of the current-to-voltage converter circuit. A floating gate device has one terminal coupled to a fixed voltage supply, and one terminal coupled to an input terminal of the voltage-to-current converter. The other input terminal of the voltage-to-current converter is coupled to the voltage reference output terminal of the programmable voltage reference circuit. Also, the voltage output terminal of the current-to-voltage converter circuit is coupled to the negative voltage input terminal of the voltage-to-current input circuit.

Abstract: A fabricated multiple layer integrated circuit in which adequate planarization is accomplished using irregularly shaped and properly spaced conductive filler features that are spaced in such a way that capacitive coupling of the conductive filler features with the active conductive regions is reduced. The overall layout area of the conductive filler features is reduced to thereby reduce capacitive coupling with active conductive above and below. In addition, a relatively small edge of the feature is closest to the active conductive in the same conductive layer thereby further reducing capacitive coupling.

Abstract: An EEPROM memory cell that includes two floating gate transistors. Each of the drain terminals of the transistors is coupled to a corresponding differential bit line. The source terminal of both transistors are coupled to a common current source or sink. Each of the control gate terminals are coupled to a corresponding word line, which may be the same as or different than the corresponding word line that the other control terminal is connected to. The floating gate transistor may be five-terminal devices that include an additional well terminal. In that case, a different set of bit lines is used to program the EEPROM memory cell as are used to read the EEPROM memory cell. While the drain terminals are coupled to the differential read bit lines, each of the well terminals is coupled to a corresponding differential program bit line.

Abstract: Amplitude detection of a baseband electrical signal. The detection may be performed by performing full wave rectification on both an in-phase portion of the electrical signal, as on a quadrature-phase portion of the electrical signal. The output signal may be generated by summing the rectified in-phases signal and the rectified quadrature-phase signal. The peak amplitude of the output signal may then be used to determine the amplitude of the original baseband signal.

Abstract: A direct conversion receiver is disclosed that converts RF signal into corresponding quadrature baseband signals without requiring conversion through an intermediate frequency. The direct conversion receiver abates local oscillator leakage, increases dynamic range and increases RF selectivity as compared to conventional direct conversion circuits. The circuit includes an in-phase branch and a quadrature-phase branch, each branch including two mixers instead of the conventional one. Each mixer is provided with balanced control signals that include a primary control signal and a complementary control signal. For each branch, the signals from the mixer pass through an operational amplifier and a low pass filter to extract the corresponding baseband signal component.

Abstract: An enhanced output impedance current mirror in which the operational amplifier includes a set of four MOSFETs having a common gate that is connected to a drain terminal of one of the differential pairs. Two of the MOSFETs reside in parallel in the current path of each of the MOSFETs of the differential pair. The differential pair MOSFET that has its drain terminal connected to the common gate also has a gate terminal that is connected to the common node between the two other MOSFETs in its current path.

Abstract: A runtime programable RS decoder that can operate on multiple pieces of data during one clock cycle in order to generate, reduce, and evaluate polynomials involved in the decoding of an RS code, and which allows a user to choose the RS code after the circuit has been implemented.

Abstract: The invention relates to transport techniques and can be used for protecting passengers and a pilot in a cabin of an aircraft or another transport means against intense light, in addition to an auxiliary arrangement for moving mobile furniture elements. The dimming device comprises a blind and a mechanism for moving the blind, including guides for translational displacement of the blind and axial connecting elements of said mechanism. Intermediate non-rigid elements like, for example, a self-adhesive gearing band are arranged between contacting surfaces of the blind and the guides. The device ensures smooth displacement of the blind by means of decreasing friction force between the contacting elements and reduces noise occurring while the device is in use.

Abstract: A bandgap reference that generates a temperature stable DC voltage by using a corrective current. The corrective current is generated by a series of differential pairs that are controlled by both positive temperature shift gate voltage on one transistor, as well as a negative temperature shift gate voltage on the other transistor. As temperature changes and crosses the crossing point at which the current is split evenly through both transistors, the current change is more abrupt. The crossing points of each of the differential pairs may be appropriately selected so as to generate a high resolution corrective current. The various current contributions are summed to form the total corrective current, which tends to be quite accurate due to the abrupt crossing points. The corrective current is then fed back into the circuit so as to compensate for much of the temperature error.

Abstract: A bandgap voltage reference uses multiple PTAT voltage reference circuits (also called PTAT sources) coupled in series to generate a final PTAT voltage. A current-biased base-emitter region of a bipolar transistor is coupled between the final PTAT voltage and an output terminal of the bandgap voltage reference so as to add the base-emitter voltage to the final PTAT voltage to thereby generate a stable bandgap voltage reference. By using multiple PTAT voltage reference in series, the need for a resistor ratio is reduced (or even eliminated) thereby reducing the size of the resistors that generate the resistor ratio (or eliminate the need for the resistors entirely).

Abstract: Transconveyance amplifiers, and more specifically charge transfer amplifiers, are included in analog-to-digital converters. Transconveyance amplifiers are used in averaging and interpolation circuits that facilitate converting an analog signal into a meaningful digital representation of the analog signal. Due to the characteristics of charge transfer amplifiers power dissipation in averaging and interpolation circuits is significantly reduced. Coupling capacitors associated with charge transfer amplifiers are utilized as analog sample and hold circuits for holding an analog signal while fine reference voltages settle. Thus, the need for separate sample and hold circuits is eliminated. A novel timing scheme allows an increased number of clock partitions for fine reference voltages to settle, thus providing for increased operational frequency.

Abstract: A method for detecting an interaction between two tester proteins. In a cell incapable of activating a Ras protein, two nucleic acid sequences are expressed. One sequence encodes for a fusion protein comprising a mutant Ras protein incapable of localizing at the cell membrane and not requiring an exchange factor fused to one of the tester proteins. The other sequence encodes for the other tester protein fused to a plasma membrane localization domain. An interaction between the two fusion proteins leads to the expression of a functional Ras protein that is tested as an altered cell phenotype.

Abstract: A charge transfer amplifier that performs amplification without a selective coupling to a precharge reference voltage. In lieu of the selective precharge coupling, the drain of the PMOS transistor is selectively coupled to Vss during the reset and precharge phases. In addition, the drain of the NMOS transistor is selectively coupled to Vss during the reset phase, and is selectively coupled to Vdd during the precharge phase. The drain of the PMOS transistor is capacitively coupled through a first intermediate capacitor to the output terminal of the charge transfer amplifier. The drain of the NMOS transistor is capacitively coupled through a second intermediate capacitor to the output terminal. During the amplify phase, the drains of the NMOS and PMOS transistor are permitted to float except for any charge flow through the respective transistor.

Abstract: This invention is to provide yarns including fishing lines which contain ultra-high molecular weight polyethylene filaments with low elongation rate, adjustable specific gravity and excellent abrasion resistance, and to provide a method for manufacturing the same.

Abstract: This invention relates to a method for tungsten chemical vapor deposition on a semiconductor substrate, comprising positioning said substrate within a deposition chamber, heating said substrate and depositing under low pressure the tungsten on the substrate by contacting the latter with a mixture of gases flowing through the deposition chamber comprising tungsten hexafluoride (WF6), hydrogen (H2) and at least one carrier gas. The mixture of gases comprises also silane (SiH4) with such a flow rate that the flow ratio WF6/SiH4 is from 2.5 to 6, the flow rate of WF6 being from 30 to 60 sccm, while the pressure in the deposition chamber is maintained from 0.13 to 5.33 kPa (1 and 40 Torr).

Abstract: The invention relates to an integrated high power sine wave carrier circuit for outputting a low distortion high power sine wave. The circuit is used for antennas, and especially for antennas in automotive appliances. The circuit comprises a H-bridge (2) with matched power transistors (4, 6, 8, 10), a sine generator (24) for driving the H-bridge and a regulator (22) for sensing the power applied to the antenna and controlling the current amplitude of the sine wave output by the sine generator. The circuit operates under partial time-working, whereby the integration circuit is turned on or off. The circuit therefore comprises a shutdown pin, for shutting the circuit down in order to allow cooling. The partial time operation allows the circuit to be integrated on a single die.

Abstract: A memory initialization circuit includes one or more duplicated pairs of bit lines, which may be used to initialize the memory cells of a memory array to different logical values. When an initialization signal is asserted on the initialization circuit, the individual bit lines in the pair of bit lines are set to opposite logical values, for instance setting one bit line to a logical zero and the other to a logical one. This occurs without regard to external data values received by the circuit. When the initialization signal is removed, individual bit lines in a duplicated pair carry identical values, which may be equal to external data values that are received by the circuit. Thus, after initialization, memory cells function as if duplicated pairs were not included in the circuit. A memory array may be initialized to a predetermined pattern by coupling different combinations of memory cells to different bit lines from duplicated pairs.