Abstract: A method for forming a pre-metallization layer on an underlying micro-structure, and a corresponding micro-structure formed by the method. The micro-structure may be a semiconductor circuit and/or a Micro-Electro-Mechanical Systems (MEMS) device. A first layer of undoped silicate glass is deposited on a micro-structure. Then, a layer of phospho silicate glass is deposited on the first layer of undoped silicate glass. This combination is then densified by applying a temperature to the combination that is sufficient to densify the layer of phospho-silicate glass, while being below the glass flow temperature. After densification, a second layer of undoped silicate glass is deposited on the densified layer of phospho silicate glass. Finally, the upper surface of the second layer of undoped silicate glass is polished using a chemical mechanical polishing process. The result is a dielectric layer of high density and low stress, and that reduces soft errors and defects.

Abstract: A low power analog-to-digital channel includes a decimation filter coupled to a sigma-delta modulator. Various embodiments include a decimation filter including an output and a sigma-delta modulator coupled to the output of the decimation filter, where a clock frequency applied to the decimation filter is approximately a integral multiple of a sampling frequency of the sigma delta modulator. In an embodiment, the sigma-delta modulator includes one or more successive approximation converters. In an embodiment, the sigma delta modulator includes one or more area efficient integrators.

Abstract: A direct conversion circuit that not only down-converts the received modulated signal using a down-converting mixer into a baseband signal, but also, after performing a passive low pass filtering to remove higher-order components, performs up-conversion of the baseband signal using an up-converting mixer. Active elements such as highly sensitive amplifiers do not operate on the baseband signal itself, but on the up-converted version of that baseband signal, thereby reducing the 1/f noise introduced by those active elements. The downstream circuitry after the up-conversion may be coupled by intervening capacitors since the downstream circuitry is operating on a higher frequency signal. Accordingly, the DC offset introduced by the downstream active elements is reduced.

Abstract: Systems, devices, and methods are provided to inhibit apparent amplitude modulation in non-linear processing that causes distortion in a processed signal. One aspect of the invention includes a hearing aid. The hearing aid includes a microphone to receive an input signal, a speaker to reproduce the input signal, and a processor. The processor processes the input signal using a gain. The processor includes an inhibitor, which inhibits distortions, and an adjuster, which adjusts the gain. The inhibitor acts to smooth an envelope of the input signal to inhibit undesired modulation. The adjuster adjusts the gain if the envelope is either above or below a threshold. The hearing aid further includes a compression recapture system to supply the compressed portion of the input signal to more closely reproduce the actual input signal.

Abstract: Method and system for real-time speech recognition is provided. The speech algorithm runs on a platform having an input-output processor and a plurality of processor units. The processor units operate substantially in parallel or sequentially to perform feature extraction and pattern matching. While the input-output processor creates a frame, the processor units execute the feature extraction and the pattern matching. Shared memory is provided for supporting the parallel operation.

Abstract: A device for generating an artificial constriction in the gastrointestinal tract comprises a band (1), which can be placed annularly about a particular portion of the gastrointestinal tract, and a closure device (2) for connecting the end regions of the band (1), placed annularly about the portion of the gastrointestinal tract, which, in the closed state of the closure device (2) encompasses a throughlet opening (6), the band (1) comprising a hollow chamber (14) fillable with a filling medium and extending at least over a large portion of the length of the band (1), and upon filling the hollow chamber (14) a wall (11), delimiting the throughlet opening (6) of the band (1), extends in the direction toward the axis (7) of the throughlet opening decreasing the size of the throughlet opening. The device comprises further a foamed material body (13), connected with the band (1), which adjoins the surface (12), facing away from the throughlet opening (6), of the wall (11) delimiting the throughlet opening.

Abstract: A method and system for synthesizing audio speech is provided. A synthesis engine receives from a host, compressed and normalized speech units and prosodic information. The synthesis engine decompresses data and synthesizes audio signals. The synthesis engine can be implemented on a digital signal processing system which can meet requirements of low resources (i.e. low power consumption, lower memory usage), such as a DSP system including an input/output module, a WOLA filterbank and a DSP core that operate in parallel.

Abstract: A receiver circuit that includes a direct conversion receiver that receives a modulated signal, and generates an in-phase differential signal and a quadrature-phase differential signal. The receiver circuit includes an in-phase branch that processes the in-phase differential signal, and a quadrature-phase branch that processes the quadrature-phase differential signal. Each branch includes an amplifier and a summer. The amplifier is configured to receive and amplify the respective in-phase or quadrature-phase differential signal. The summer receives the resulting amplified differential signal and sums the signals to generate a single signal. A log amplifier receives the summed in-phase and quadrature-phase signal, and generates an RSSI signal that is proportional to the log of the difference between the two summed signals. The data may then be extracted based on the amplitude of the RSSI signal.

Abstract: An adaptive signal processing system for improving a quality of a signal. The system includes an analysis filterbank for transforming a primary information signal in time domain into oversampled sub-band primary signals in frequency domain and an analysis filterbank for transforming a reference signal in time domain into oversampled sub-band reference signals. Sub-band processing circuits process the signals output from the filterbanks to improve a quality of an output signal. A synthesis filterbank can combine the outputs of the sub-band processing circuits to generate the output signal.

Abstract: A closed loop DC-to-DC converter circuit that includes an open loop DC-to-DC converter circuit configured to provide charge on its output terminal. A voltage-controlled inverse-resistance component is coupled to the output terminal of the open loop DC-to-DC converter circuit, such that the greater the voltage differential across the component, the lower the resistance provided by the component. A feedback system provides a signal to a control terminal of the open-loop DC-to-DC converter circuit that is dependent on the current provided through the voltage-controlled inverse-resistance component. Specifically, the signal provided by the feedback system causes the open loop DC-to-DC converter circuit to generate more current on the output terminal when there is less current passing through the voltage-controlled inverse-resistance component, and less or no current on the output terminal when there is more current passing through the voltage-controlled inverse-resistance component.

Abstract: An EEPROM cell that combines a FET transistor and a capacitor. The transistor has a well that is shared by potentially all of the EEPROM cells in the array thereby reducing size. A gate terminal is formed over the well. Source and drain terminals are formed in the well. The well is isolated from the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal, and may be oppositely doped from the gate terminal to improve retention. The second terminal is formed by a second well that is underneath the first terminal and isolated from the first terminal. The capacitance may be increased without area increase by forming a metal layer over the first terminal and separated from the first terminal by a thick dielectric layer, and connected to the second well via a conductive via.

Abstract: A measurement method or system for measuring a physical value comprises, during a same clock cycle, forming an input signal, a reference signal and an offset signal, the input signal including a parasitic value and a useful measurement value. A relationship between the input signal where the parasitic value has been cancelled out, and the reference signal is derived. From this relationship, a value relating to the physical value is determined. The input signal, reference signal and offset signal are respectively associated with an input element, a reference element and a parasitic element. All elements have a common driving signal, and the parasitic value is depending on the common driving signal.

Abstract: This invention is to provide yarns including fishing lines which contain ultra-high molecular weight polyethylene filaments with low elongation rate, adjustable specific gravity and excellent abrasion resistance, and to provide a method for manufacturing the same.

Abstract: An operational amplifier with two differential pairs coupled to different current sources. The gate terminals of the transistors in the first differential pair are used as input terminals providing common mode input for most of the rail-to-rail voltage. The bulk terminals of the transistors in the second differential pair are used as input terminals providing common mode input for the remainder of the rail-to-rail voltage to thereby accomplish full rail-to-rail common mode. By using the bulk terminals of the field effect transistors in the second differential pair, rather than the gate terminals, as the input terminal, the operational amplifier may be constructing in a single well, thereby being compatible with standard digital CMOS processes. Alternatively, the bulk-driven transistors may be replaced with gate-driven depletion type transistors. The high voltage transistors in the output stage further reduce the offset voltage of the operational amplifier.

Abstract: The present invention is a method of optical tracking sensing using block matching to determine relative motion. The method includes three distinct means of compensating for non-uniform illumination: (1) a one-time calibration technique, (2) a real-time adaptive calibration technique, and (3) several alternative filtering methods. The system also includes a means of generating a prediction of the displacement of the sampled frame as compared to the reference frame. Finally, the method includes three cumulative checks to ensure that the correlation of the measured displacement vectors is good: (1) ensuring that “runner-up” matches are near the best match, (2) confirming that the predicted displacement is close to the measured displacement, and (3) block matching with a second reference frame.

Abstract: A system and method of improving signal intelligibility over an interference signal is provided. The system includes a psychoacoustic professor having a psychoacoustic model wherein the level of a signal-of-interest is improved so as to be audible above noise and so as not to exceed a predetermined maximum output level. The system can be combined with active noise cancellation.

Abstract: The invention relates to a method for producing pure melamine in a high-pressure method. According to said method, in the first stage, the melamine melt is brought into contact with hot NH3 and NH3 from the second stage and in the second step is brought into contact with cold NH3 in such a way that it is cooled to a temperature, which is 1–30° C. above the pressure-dependent melting point of the melamine, before being optionally rested in a third stage and subsequently treated in various ways.

Abstract: A differential signal output driver circuit having four switching transistors and having a bias transistor that shields each of the switching transistors from the corresponding output terminal thereby blocking the Miller capacitance of the switching capacitor from generating overshoot or undershoot in the output differential voltage. Also, the output driver circuit may be driven by a differential skew cancellation circuit that generates a balanced differential signal to drive the switching transistors to further improve signal integrity. The signal path for generating each signal in the differential signal goes through a similar structure thereby ensuring similar slew in each differential signal provided to the output driver circuit.

Abstract: A dynamic phase adjustment circuit that includes a multi-tap delay line that receives a clock input signal. The multi-tap delay line includes an initial portion that is adjustable, and final portion after the adjustable portion. A number of registers receive the same data. However, the clock signal that causes the registers to sample is received from a corresponding delay element in the final portion of the multi-tap delay line. An edge detect and data decision circuit receives the sampled data values from each of the registers. Sampling resolution is improved over the PLL-based dynamic phase adjustment circuit since the clock signal is delayed using delay elements, which can be made with relatively small delays. Furthermore, the circuit does not contain excessive circuit elements thereby allowing the dynamic phase adjustment circuit to be contained in a small area.

Abstract: A monotonic digital-to-analog converter (DAC) for converting a digital input signal into an analog output signal comprises: an input node for receiving the digital input signal having at least M+L bits, an output node for delivering the analog output signal corresponding to the received digital input signal, a coarse conversion block comprising current sources and first switching means for converting M more significant bits of the digital input signal into a coarse block output current, a fine conversion block comprising a current divider and second switching means for converting L less significant bits of the digital input signal into a corresponding current value, the fine conversion block having means for receiving current from a first unselected current source of the coarse conversion block, and a first cascode means for active cascoding the coarse block output current, a second cascode means, for active cascoding the current from the first unselected current source.