Abstract: An electric contact comprises a main body consisting of a copper-based alloy or of stainless steel and a contact layer consisting of a gold-based alloy. The contact layer has a thickness of at least 0.3 ?m and consists of gold with a content of 0.5 percent by weight to 15 percent by weight of one or more platinum group metals, and that an intermediate layer consisting of silver or of a silver-based alloy or of nickel is provided between the main body and the contact layer. The contact layer is preferably applied on the main body by a PVD process.

Abstract: This invention describes a practical application of noise reduction in hearing aids. Although listening in noisy conditions is difficult for persons with normal hearing, hearing impaired individuals are at a considerable further disadvantage. Under light noise conditions, conventional hearing aids amplifying the input signal sufficiently to overcome the hearing loss. For a typical sloping hearing loss where there is a loss in high frequency hearing sensitivity, the amount of boost (or gain) rises with frequency. Most frequently, the loss in sensitivity is only for low-level signals; high level signals are affective minimally or not at all. A compression hearing aid is able to compensate by automatically lowering the gain as the input signal level rises. This compression action is usually compromised under noisy conditions.

Abstract: Silicon-based voltage reference circuits that generate a temperature independent voltage reference that is less than even the silicon bandgap potential. The voltage reference circuit includes a diode-connected metal-silicon Schottky diode that is biased with a current. In this configuration, the anode terminal of the Schottky diode is a CTAT voltage source in this configuration. The anode terminal has a voltage at zero degrees Kelvin at the barrier height of the Schottky diode, which may differ depending on the metal chosen, but in most cases is less than the bandgap potential of silicon. The voltage reference circuit also includes a PTAT voltage source. The PTAT voltage may be generated in a variety of ways. An amplifier amplifies the PTAT voltage, and a summer adds the CTAT voltage to the amplified PTAT voltage to generate the temperature stable voltage reference.

Abstract: A braided cord consisting of braided filaments or a twisted cord of filaments in which at least a part of the filaments are high tenacity multifilaments, and the rest of the filaments are monofilaments, which is preferably used as a serving for an archery bowstring.

Abstract: Reactive sensors typically exhibit nonlinear response to temperature variation. Systems and methods are disclosed for compensating for the nonlinear and/or temperature dependent behavior of reactive sensors and for calibrating the post-compensation output signals relative to known samples of the physical parameter under measure. One call of embodiments includes a housing containing at least part of a reactive sensor, a monolithic integrated circuit and a timing reference. The integrated circuit includes a waveform generator for generating a sensor exciting signal, a detector for detecting the response of the sensor to the combination of the exciting signal and the under-measure physical parameter, a temperature compensating unit and the Pade Approximant nonlinearity compensating unit are tuned by use of digitally programmed coefficients. The coefficients calibrate the final output as well as compensating for nonlinearity and temperature sensitivity.

Abstract: A diversity receiver circuit that adaptively selects a variable number of one or more antennas for use in improving signal quality. Each antenna is provided its own receiver that each generates a representation of a received signal. This adaptive selection offers high dynamic adaptability in using the appropriate antennas and receivers at the appropriate time to thereby improving signal-to-noise ratio. The receivers may be direct conversion receivers that implement up-conversion of the baseband signal to reduce DC offset and 1/f noise characteristic of direct conversion architectures.

Abstract: Methods for protecting the sidewall of a metal interconnect component using Physical Vapor Deposition (PVD) processes and using a single barrier metal material. After forming the metal interconnect component, a single barrier metal is deposited on its sidewall using PVD. A subsequent anisotropic etching of the barrier metal removes the barrier metal from the horizontal surface except for some that still remains on the top surface of the metal interconnect layer. A dielectric layer is then formed over the metal interconnect component and the barrier metal. The unlanded via is etched through the dielectric layer to the metal interconnect component, and then filled with a second metal to thereby allow the metal interconnect component to electrically connect with one or more upper metal layers.

Abstract: A current measurement circuit that measures current passing through two loads. The circuit includes a differential output transconductance amplifier. One current output terminal pf the amplifier receives the current from the first load with the first voltage input terminal coupled to that current output terminal. The second current output terminal provides a current to the second load with the second voltage input terminal coupled to the second current output terminal with the current provided at the second output terminal being approximately equal to the current received at the first current output terminal. The transconductance amplifier provides a copy current on the third current output terminal this is approximately equal to at least one of the other output currents. That copy current is then directly measured, rather than the actual current passing through the loads.

Abstract: Disclosed is an Amplifier (7) comprising an output driver with a first output stage (4) and a second output stage (5), where an input signal is applied non-inverted to the first output stage and inverted to the second output stage, characterized in that said input signal is applied with delay to one of the output stages (4, 5).

Abstract: A two-dimensional matrix decoder of a digital-to-analog converter comprises an array of current cells, the cells having a current source means or a current divider means and a switching means, all cells being activatable in a pre-determined sequence. The matrix decoder comprises: a selection means outputting a first selection signal for selecting a cell, a cell state signaling means outputting a cell state signal determining whether a cell comes before or after the selected cell in the pre-determined sequence, and matrix logic associated with each cell for generating a control signal suitable for controlling the switching means of that cell for switching current from the current source means or current divider means of that cell to at least one of a first node or a second node, the control signal being generated depending on the first selection signal and the cell state signal.

Abstract: A digitally controlled impedance driver circuit including a number of fingers, some of which having FETs and series resistors sized in binary or other differential ratios, and some of the higher power FETs being sized in equal ratio and perhaps sharing a series resistor. A DCI controller circuit periodically determines a configuration of the DCI driver circuit that would result in the DCI driver circuit approximating a target impedance. Each time the DCI controller circuit does this, a comparator determines if the impedance of the DCI driver circuit should be increased or decreased. A noise attenuation circuit turns off (or on) only one of the high power fingers if the controller circuit determines that more (or less) impedance is needed even if turning off (or on) only one of the fingers would not result in the configuration of the DCI driver circuit determined by the controller circuit.

Abstract: Protection circuits (1) to be located between power supplies (2) and further circuitries (20,30) for protecting further circuitries (20,30) against voltage irregularities and comprising main transistors (7) coupled to switching circuits (10) for rendering main transistors (7) operative/non-operative can be made more allround by providing them with comparators (11) for controlling gate voltages of main transistors (7) via switches (12,13) to get protection against small negative voltage pulses and voltage fluctuations. Said switches (12,13) comprise two switches (12,13) for interrupting a reference voltage generated by a reference voltage source and for supplying a nearby ground voltage to said gate. A diode (14) between switch (13) and gate allows negative voltages at said gate for simplifying the introduction of further stages. Thick oxide transistors (15) protect further circuitries (20,30) and main transistors (7) against large negative voltage pulses.

Abstract: An integrated overvoltage and reverse voltage protection circuit. The protection circuit includes a field-effect transistor having a source terminal coupled to an input terminal of the protection circuit, and a drain terminal coupled to an output terminal of the protection circuit. A resistor is coupled between the source terminal and the body terminal of the field-effect transistor to inhibit reverse current flow during a reverse voltage condition. A voltage-current dependent circuit is coupled between the gate terminal and the source terminal of the field-effect transistor, and is configured to apply a voltage between the gate terminal and the source terminal that is dependent on the current passing through the voltage-current dependent circuit. A current application circuit is coupled to the voltage-current dependent circuit and is configured to apply a current that limits or even altogether stops an applied overvoltage condition from reaching a load circuit.

Abstract: Systems and methods are disclosed for distributing memory within one or more regions of circuitry that perform logic functions (or other types of functions that require dense interconnect structures) on an integrated circuit. The distributed memory reduces high density routing congestion, allows increased logic utilization, and provides areas for additional interconnect structure. Various techniques are also disclosed for accessing the memory.

Abstract: An integrated overvoltage and reverse voltage protection circuit that includes two p-channel double-sided extended drain transistors coupled to a high voltage source, each having their n-well coupled through a resistor to the high voltage source. For voltage regulation, a voltage divider is coupled in series with a first of these transistors, while the drain of the second transistor is coupled to the gate of the first transistor. For voltage blocking, the voltage divider may span the entire supply voltage. An n-channel transistor couples the second p-channel transistor to a low voltage source. A middle node in the voltage divider is coupled to one input of a comparator, with a reference voltage coupled to the second input. The comparator output drives the gate terminal of the n-channel transistor. A load to be protected may be disposed in parallel with the voltage divider.

Abstract: A dual differential-input operational amplifier that includes six PMOSFETs having their source terminals coupled to a high voltage. A seventh and eighth PMOSFET have their source terminals coupled to a current source. Four NMOSFETs have their source terminals coupled to a low voltage. A fifth and sixth NMOSFET have their source terminals coupled to a current sink. The various PMOSFETs and NMOSFETs are coupled together such that the gate terminals of the fifth NMOSFET and eighth PMOSFET receive a first input of the differential input, and such that the gate terminals of the sixth NMOSFET and the seventh PMOSFET receive a second input of the differential input. The operational amplifier may be vertically inverted, or implemented by bipolar transistors, with cascoding devices, and with a second stage in the form of an inverter.

Abstract: An electrostatic discharge (ESD) protection circuit for the protection of an electronic circuit from an ESD event. The electronic circuit, in operation, is provided with a supply voltage and a reference voltage (typically electrical ground) via voltage terminals and/or power supply buses. The protection circuit includes two bipolar transistors in series, where the transistors are coupled between the supply voltage terminal/bus and the reference voltage terminal/bus. The bases of the transistors are coupled via a connection including two resistors in series, where the connection point between the two resistors is coupled with the connection point between the two transistors.

Abstract: A method for making interconnect structures, particularly in a semiconductor integrated circuit, is described. The method comprises the steps of: forming a conductive layer; forming of an insulating layer above said conductive layer; creating a plurality of holes in said insulating layer and filling the holes with tungsten thereby forming tungsten plugs, such that said tungsten plugs are in electrical contact with the conductive layer. A patterned metallisation layer that overlies said insulating layer (is formed by means of following steps: forming a continuous metallisation layer, forming an organic mask, etching in plasma said continuous metallisation layer, removing the organic mask in a dry way, and immersing the obtained wafer including the layers (3, 4, 5) and the tungsten plugs in a cleaning solution to remove the post-etching residues. Before immersing into said cleaning solution, the wafer is submitted to a plasma treatment containing F, H or a mixture of F and H.

Abstract: A complementary differential amplifier includes two differential amplifiers. Each differential amplifier includes two input FETs (or bipolar transistors) having gate terminals coupled to the input terminals of the complementary differential amplifier. Two current load p-type field-effect transistors are each coupled in series between one voltage source and a drain terminal of a respective input FET. A current source FET is coupled in series between a common source terminal of the two input n-type field-effect transistors and a low voltage source. Only two FETs are needed to bias all of the current load and source FETs. A complementary folded cascode stage as well as an inverter stage may also be included.

Abstract: A switched capacitor voltage reference circuit that has a transconductance circuit that receives the output of the amplifier, and then outputs a current that depends on its input voltage. This may be accomplished using a charge pump that is controlled by the amplifier output. The transconductance circuit provides a reference voltage at the output terminal of the switched capacitor generation circuit. A capacitor capacitively couples the output terminal of the switched capacitor circuit to the inverting terminal of the amplifier during the generation phase. By adjusting the capacitances of the various capacitors, the level and temperature dependence of the generated reference voltage may be controlled. Also, the charge pump often allows for reference voltages that are greater than the supply voltage.