Abstract: Micro lead frame (MLF)-type semiconductor packages that allow the semiconductor packages to be stacked on top of each other. One aspect of the semiconductor package includes a leadframe, a plurality of electrical connectors, a semiconductor chip, and a sealing material for encapsulating the above components. The leadframe has a plurality of leads, with each one of the plurality of leads running from the top of the semiconductor package to the bottom of the semiconductor package. Each one of the plurality of leads has a top portion protruding from the top surface of the semiconductor package and a bottom portion protruding from the bottom surface of the semiconductor package. The leads allow for electrical connection of a second semiconductor package placed on top of the first semiconductor package. Further, the protruding parts of the leads form a space between the stacked semiconductor packages for improved heat dissipation.

Abstract: A method of packaging a device is disclosed. In one embodiment, a substrate including a common voltage plane and a mounting region is provided, with the device mounted to the mounting region. An electrically conductive dam structure is disposed on the surface of the substrate with the electrically conductive dam structure being electrically coupled to the common voltage plane and circumscribing a perimeter of the mounting region. An electrically insulating encapsulant at least partially fills a pocket defined by the substrate and the electrically conductive dam structure, the electrically insulating encapsulant contacting the electrically conductive dam structure. An electrically conductive encapsulant is provided that overlies the electrically insulating encapsulant, the electrically conductive encapsulant being coupled to the electrically conductive dam structure.

Abstract: An image sensor package includes a substrate and an image sensor mounted to the substrate. Bond pads of the image sensor are wirebonded to interior traces on the substrate by bond wires. An encapsulant encloses the bond wires, the encapsulant being formed of a first optically curable material that has been cured. A lid adhesive mounts a lid to the substrate, the lid adhesive being formed of a second optically curable material that has been cured. During fabrication, the first and second optically curable materials are cured rapidly without heating to form the encapsulant and the lid adhesive, respectively, thus minimizing the fabrication cost of the image sensor package.

Abstract: In a leadframe type of semiconductor package, the internal electrical interconnectability of and signal routing between multiple dies laminated in a stack with the die paddle of the leadframe is substantially enhanced by laminating an “interposer” in the stack. The interposer comprises a dielectric layer and a metallic layer patterned to include wire bonding pads arrayed around the periphery of a surface thereof, and circuit traces interconnecting selected ones of the wire bonding pads in a single plane across the horizontal span of the interposer. In packages having multiple dies and relatively few leads, the bonding pads and circuit traces can be flexibly arranged on the interposer by the package designer to substantially increase the number and routings of internal electrical interconnections otherwise possible between the dies and between the dies and the leads of the package.

Abstract: A simple, inexpensive method and apparatus are provided for increasing the thickness of a body molded on a semiconductor package without the need for a new mold, or for reworking the parts of an existing mold. The method includes providing a mold having parts that engage each other at respective interfacial surfaces, and a shim having a selected thickness and an opening through an interior portion thereof. The shim is interposed between the interfacial surfaces of the mold parts such that the mold parts are spaced apart by the thickness of the shim, and such that the mold parts and the shim opening define a cavity in the mold. The length and width of the cavity of the mold thus remain the same, while the height of the cavity, and hence, the thickness of the molded body, is increased by the thickness of the shim.

Abstract: A thermally enhanced, chip-scale, Lead-on-Chip (“LOC”) semiconductor package includes a substrate having a plurality of metal lead fingers in it. A semi-conductor chip having an active surface with a plurality of ground, power, and signal connection pads thereon is mounted on an upper surface of the substrate in a flip-chip electrical connection with the lead fingers. A plurality of the ground and/or the power connection pads on the chip are located in a central region thereof. Corresponding metal grounding and/or power lands are formed in the substrate at positions corresponding to the centrally located ground and/or power pads on the chip. The ground and power pads on the chip are connected to corresponding ones of the grounding and power lands in the substrate in a flip-chip connection, and a lower surface of the lands is exposed to the environment through a lower surface of the semiconductor package for connection to an external heat sink.

Abstract: A method includes modifying wettable regions of a leadframe with a laser to form non wettable barriers. Wettable pads are defined with the non wettable barriers. Since the non wettable barriers are formed in a single automated step with the laser, the non wettable barriers are formed at low cost. During flip chip mounting of an electronic component to the leadframe, the non wettable barriers confine solder to the wettable pads. This results in consistent and reliable solder bump formation.

Abstract: A method is disclosed for manufacturing chip-scale semiconductor packages at a wafer-scale level using wafer mapping techniques. In the method, a semiconductor wafer and/or a circuit substrate, each respectively comprising a plurality of individual chips and circuit pattern units, is/are pre-tested and discriminated in terms of the quality and/or grade of each individual chip unit and/or circuit pattern unit contained therein. The test results are marked on the lower surface of each chip unit and/or on each pattern unit. The substrate is laminated to the wafer to form a laminated assembly prior to performing the packaging process, which typically includes a wire bonding step, an encapsulation step and a solder ball welding step. A plurality of connected package units are thereby formed in the laminated substrate-wafer assembly. The package units are then singulated from each other and the laminated assembly by a cutting process.

Abstract: An electronic device, such as a sensor die, is packaged by first forming a hole through a substrate. The hole is made large enough to position the entire electronic device within the hole. A tape is then applied to the second surface of the substrate to cover a second side of the hole, thereby creating a tape surface at the bottom of the hole. The electronic device is then positioned within the hole such that the electronic device is in contact with, and adhered to, the tape surface at the bottom of the hole. Electronic connections are made between the electronic device and the substrate and a layer of encapsulant is applied. In one embodiment, the electronic device is a sensor die and an optical element is positioned over an active region of the sensor die before the encapsulant is applied. The encapsulant then surrounds and holds the optical element in position over the active region of the sensor die.

Abstract: Integrated circuit packages that may be easily stacked one on top of the other are disclosed. The package includes a molded plastic body having metal-coated interconnection posts on both its upper and lower surfaces. An integrated circuit is mounted on the upper surface. Metal traces on the upper surface electrically connect each bonding pad on the integrated circuit to a one of a plurality of groups of four interconnection posts on the upper surface. Vias through the substrate electrically connect each group of four posts on the upper surface to an interconnection post on the lower surface of the package. Two or more packages can be stacked and electrically connected by wedging the lower posts of a top package between each group of four posts on the upper surface of a lower package. The lower posts of the lower package may be soldered to a conventional printed circuit board, or may be mounted on a mounting substrate that also has corresponding groups of four interconnection posts.

Abstract: Methods for forming packages for housing an integrated circuit device are disclosed. In one embodiment, a plastic sheet having an first surface is provided. An array of package sites is formed on the first surface of the plastic sheet. The package sites each include a metal die pad and leads surrounding the die pad. The package sites may be formed by applying a first metal layer on the first surface of the plastic sheet, and then applying a second metal layer in a pattern that defines the die pads and leads of the package sites. The first metal layer is then selectively etched using the second metal layer as an etch mask. Next, an integrated circuit die is placed on each die pad of the array. The die is electrically connected to the leads surrounding the respective die pad. An encapsulant is applied onto the first surface of the plastic sheets so as to cover the package sites.

Abstract: A protective layer includes a polymerized region, which forms a cavity in an interior surface of the protective layer. The protective layer is mounted to a micromachine chip such that an active area of the micromachine chip is located within the cavity of the protective layer. The protective layer protects the active area during front-side or back-side singulation of the micromachine chip from a micromachine substrate.

Abstract: An RF shielded package includes a heat sink having a plurality of spring elements. The spring elements press the heat sink against a mold half during encapsulation to prevent encapsulant from leaking between the heat sink and the mold half. Further, the spring elements ground the heat sink to shield an electronic component from RF radiation.

Abstract: Integrated circuit device packages and substrates for making the packages are disclosed. One embodiment of a substrate includes a planar sheet of polyimide having a first surface, an opposite second surface, and apertures between the first and second surfaces. A planar metal die pad and planar metal are attached to the second surface of the polyimide sheet. The apertures in the polyimide sheet are juxtaposed to the leads. A package made using the substrate includes an integrated circuit device mounted above the first surface of the polyimide sheet opposite the die pad. Bond wires are connected between the integrated circuit device and the leads through the apertures in the polyimide sheet. An encapsulant material covers the first surface of the polyimide sheet, the integrated circuit device, the bond wires, and the apertures. The die pad and leads are exposed at an exterior surface of the package.

Abstract: Disclosed is a matrix type printed circuit board (PCB) for semiconductor packages having a structure including a plurality of PCB units arranged in a matrix array having at least two rows in such a fashion that the mold runner gates of adjacent PCB units respectively arranged in adjacent rows while being arranged in the same column communicate with each other by an integrate mold runner, thereby being capable of allowing an increased number of PCB units to be simultaneously processed in each process involved in the fabrication of semiconductor packages, so that a great improvement in productivity is achieved. In particular, it is possible to allow an increased number of PCB units to be simultaneously molded in a resin encapsulate molding process, thereby achieving a great improvement in the efficiency of the resin encapsulate molding process.

Abstract: Semiconductor packages including at least one semiconductor chip and at least one electronic discrete device, such as a transistor, oscillator, optical sensor, resistor, capacitor, or inductor, are disclosed. The semiconductor chip and the discrete device are electrically coupled to each other, and are encapsulated within a protective encapsulant material. The semiconductor chip and the discrete device are disposed either in an aperture through the substrate or in a pocket of the substrate, thereby allowing for a thin package, even where the discrete device is taller (e.g., 1.5 to 5 times taller) than the semiconductor chip and/or substrate.

Abstract: Chip-size semiconductor packages (“CSPs”) containing multiple stacked dies are disclosed. The dies are mounted on one another in a stack such that corresponding ones of the vias in the respective dies are coaxially aligned. An electrically conductive wire or pin is in each set of aligned vias and soldered to corresponding ones of the terminal pads. The pins include portions protruding from the stack of dies that serve as input-output terminals of the package. Heat spreaders can be interleaved between the stacked dies to enhance heat dissipation from the package.

Abstract: A leadframe includes a lead. The lead includes a wettable pad and a wettable lead surface. A non wettable barrier separates the wettable pad from the wettable lead surface, the non wettable barrier being formed from a modified portion of the leadframe. Solder wets only the wettable pad during formation of a solder bump between the wettable pad and a bond pad of electronic component flip chip mounted to the leadframe. This results in consistent and reliable solder bump formation. Further, the non wettable barrier is formed in a single automated step with a laser and thus at low cost.

Abstract: A method of fabricating a flip chip image sensor package includes forming an aperture in a substrate and mounting an image sensor to the substrate. The image sensor is mounted such that an active area of the image sensor is aligned with the aperture. A bead is formed around a periphery of the image sensor. An aperture side of the aperture, the image sensor, and the bead define a pocket. The method further includes filling the pocket with a transparent liquid encapsulant and hardening the transparent liquid encapsulant. The hardened transparent liquid encapsulant serves as the window for the flip chip image sensor package.

Abstract: A structure for protecting a special-purpose area of an image sensor die or a micromachine die during singulation of the die from a wafer includes a protective layer that has a polymerized upper zone and an unpolymerized lower zone. At least part of the unpolymerized lower zone has an adhesive lower surface that is attached to a top surface of the wafer so that the protective layer overlies and protects the special-purpose area during either frontside or backside sawing. The unpolymerized lower zone is then entirely polymerized to make the adhesive lower surface nonadhesive to facilitate removal of the protective layer from the die.