Abstract: A thermally enhanced package for an integrated circuit, the integrated circuit having a surface with bond pads formed thereon, includes a heat sink structure attached to a central region of the integrated circuit surface inward of the bond pads. The package further includes a substrate attached to the heat sink structure. The heat sink structure includes a heat sink and first, second adhesive layers between the heat sink and the integrated circuit, substrate, respectively. The heat sink enhances heat transfer between the integrated circuit and the substrate. Further, the first, second adhesive layers decouple any difference in thermal expansion between the integrated circuit, the heat sink and the substrate.

Abstract: A method for marking poor quality printed circuit board units of a printed circuit board strip for ball grid array semiconductor packages wherein at least one degradation-indicating hole is at least partially formed in a poor quality printed circuit board unit of the strip at a region defined between an outer edge of the resin seal molding region of the unit and a cutting line formed on the printed circuit board strip to separate the unit from the strip. Even when a plurality of printed circuit board strips are packed in a vacuum under the condition in which they are stacked, there is no phenomenon that those strips in the pack are permanently deformed, for example, permanently bent. Also, there is no phenomenon that melt resin is leaked from the mold, thereby causing it to be bled out onto the upper surface of the printed circuit board strip. Since no paint is used to mark poor quality printed circuit board units, there is no problem associated with the use of the paint such as a contamination.

Abstract: Provided with a method of manufacturing a ball grid array semiconductor package using a flexible circuit board strip, which is directed to prevent minute conductive traces in the outer part of a circuit pattern formed in the flexible circuit board and thus minimize the short-circuits by forming notches on the flexible circuit board in the vicinity of the lower side ends of a resin encapsulant section by use of a punch, and pressing down the resin encapsulant section with a singulation tool to remove the carrier frame and separate the ball grid array semiconductor packages in the piece.

Abstract: A method for fabricating an LDD MOS transistor includes the steps of forming a gate conductor on a gate oxide layer formed on a substrate, forming a heavily doped source/drain region in the substrate using the gate conductor as a mask, thermally oxidizing the surface of the gate conductor and the substrate, thereby forming a reduced dimension gate conductor, and forming a lightly doped source/drain region in the substrate using the reduced dimension gate conductor as a mask. In the alternate, the method further includes the step of removing the oxidized surface of the gate conductor and the substrate using a cleaning process to expose the reduced dimension gate conductor before forming the lightly doped source/drain region. The thickness of the thermally oxidized surface of the gate conductor is about 500 .ANG..about.5000 .ANG..

Abstract: A grid array assembly method uses a flex circuitry substrate and includes providing a series of conforming flex circuitry substrates, the flex circuitry substrates include bonding pads and metallization on a first surface and, holes or vias in the substrate which define a contact pad array on the opposite surface. The substrates are tested and acceptable, then mounted on a carrier strip with longitudinally aligned apertures. The carrier strip is typically a metal such as copper. The strip with mounted substrates is then passed to a station where an IC die is mounted on the substrate first surface, wire bonds are placed from the die to the bonding pads, and the assembly is encapsulated by auto-molding to form a package body. Subsequently, interconnecting bumps are placed on the contact pads and the assembly is removed from the strip.

Abstract: A printed circuit board for a BGA semiconductor package provided at one corner thereof with a degating opening serving as a mold runner gate during a process of molding a resin seal adapted to protect the semiconductor chip and serving as a region for degating a surplus resin formed after the molding process and a method for molding a BGA semiconductor using the printed circuit board. The degating opening has an inverted triangular shape having curved lateral sides and a vertex, at which the lateral sides join together, disposed in a region for forming the resin seal, or an inverted trapezoidal shape having one end disposed in the resin seal region.

Abstract: A plurality of integrated circuit chip (IC chip) packages are fabricated simultaneously from a single insulating substrate having sections. In each section, an IC chip is attached. Bonding pads on the IC chip are electrically connected to first metallizations on a substrate first surface. The first metallizations, IC chip including bonding pads and first substrate surface are then encapsulated. Interconnection balls or pads are formed at substrate bonding locations on a substrate second surface, the interconnection pads or balls being electrically connected to corresponding first metallizations. The substrate and encapsulant are then cut along the periphery of each section to form the plurality of IC chip packages.

Abstract: A chip size semiconductor package with a light, thin, simple and compact structure having a reduced size of its semiconductor chip while having an increased number of pins and without degrading its functions. For the package, it is possible to use either the semiconductor chip having bond pads arranged on end portions of the chip or the semiconductor chip having bond pads arranged on the central portion of the chip. In either case, input/output terminals of the package are arranged in the form of an area array. Accordingly, when the package is mounted on an electronic appliance, its mounting area can be minimized, thereby achieving a compactness of the final product.

Abstract: A mold for BGA semiconductor packages which includes a height adjusting member adapted to adjust the height of the top cavity insert of the top mold or the bottom cavity insert of the bottom mold, an elastic member disposed between the height adjusting member and associated insert, clamping regions of different heights formed at its top or bottom cavity insert, or air vents having a width and depth of an optimum ratio to the area and depth of cavities, thereby being capable of maintaining an optimum and uniform clamping pressure between the top and bottom molds for a variety of PCB strips having a thickness deviation among different portions thereof or having various average thicknesses, upon molding resin encapsulants on those PCB strips, thereby achieving an improvement in the quality of finally produced packages while preventing a sweeping phenomenon of bonding wires electrically connecting a semiconductor chip to conductive traces.

Abstract: An integrated circuit package for EPROM, CCD, and other optical integrated circuit devices has a substrate base having metallized vias extending there through. An integrated circuit die is affixed to a first surface of the substrate, and is electrically connected to the metallized vias. An adhesive bead is applied onto the substrate around the die. The bead covers the side surfaces of the die, the periphery of the upper first surface of the die, and the bond wires. The bead and the upper first surface of the die form a cavity above the die. A layer of a transparent encapsulating material is deposited onto the die, within the cavity formed by the bead. The encapsulating material is hardened, and subsequently forms an exterior surface of the package. The transparent encapsulating material allows light of a selected frequency to illuminate the light sensitive circuitry of the die.

Abstract: A ball grid array semiconductor package using a flexible circuit board, in which the flexible circuit board has no conductive via hole nor solder mask while having a thin structure formed at only one surface thereof with a circuit pattern having a small length. The flexible circuit board is mounted with a metallic carrier frame to achieve an easy handling thereof, a reduction in the inductance, impedance and coupling effect of adjacent circuit patterns and an easy discharge of heat from a semiconductor chip, thereby achieving an improvement in electrical performance and an improvement in heat discharge performance. The metallic carrier frame has a plurality of openings adapted to increase the bonding force between an encapsulate and constituting elements of the package, thereby removing a bending phenomenon of the package, and a method for fabricating such a BGA semiconductor package. The invention also provides a method for fabricating such a BGA semiconductor package.

Abstract: A mounting for a flip chip integrated circuit device having a light sensitive cell is disclosed. The mounting includes an insulating substrate having an aperture between its first and second surfaces. A flip chip integrated circuit device is placed on the first surface of the substrate. A light sensitive cell of the integrated circuit device faces the aperture. Solder bumps on the integrated circuit are electrically connected to corresponding conductive metallizations on the first surface of the substrate. A transparent aperture cover is affixed to the second surface of the substrate with an adhesive bead. The aperture cover extends over the aperture, allowing light to be transmitted through the aperture cover to the light sensitive cell. The side surfaces of the aperture cover include features for locking the adhesive bead to the aperture cover.

Abstract: A package for an integrated circuit is described, as is a method of making the package. An exemplary method of making a package for an integrated circuit die includes a first step of providing an insulating substrate having a substantially planar first surface. A conductive path extends through the substrate. Step two of the method places an integrated circuit die, such as an EEPROM or a CCD or SAW integrated circuit die, on the first surface of the substrate. Step three electrically connects the integrated circuit die to the conductive path. Step three applies an imperforate bead of a viscous adhesive material on the first surface of the substrate around the die. The bead extends to a height above the first surface of the substrate greater than the height of the integrated circuit die. Step four provides a lid having a first surface.

Abstract: A package for surface acoustical wave (SAW) device includes an electrically insulative substrate having a first surface with an electrically conductive layer formed thereon. A first surface of the SAW device is attached to the electrically conductive layer. An electrically conductive adhesive bead overlies the substrate first surface and surrounds the SAW device. An electrically conductive lid defines a free space over a second surface of the SAW device, the lid being electrically connected to the electrically conductive layer by the adhesive bead and one or more tabs extending from the lid through the adhesive bead to the electrically conductive layer. The electrically conductive adhesive bead, electrically conductive layer and electrically conductive lid enclose and shield the SAW device.

Abstract: A method of forming chip bumps of a bump chip scale semiconductor package, such a package and a chip bump are disclosed. In the bump chip scale semiconductor package produced by the above method, the chip bumps are directly formed on the chip pads of a semiconductor chip. The above chip bumps are used as the signal input and output terminals of the package and are used as surface mounting joints when the chip is mounted to a mother board.

Abstract: A ball grid array semiconductor package includes a semiconductor chip mounted to the top side of a printed circuit board (PCB), having a copper circuit pattern at a position outside a chip mounting zone. A plurality of bond wires electrically connect the chip to the copper circuit pattern. A rectangular ring-shaped metal heat spreader is attached to the PCB surrounding the chip, with the outer periphery of the ring substantially coextensive with the outer periphery of the PCB. A molding compound is provided in a zone inside the heat spreader thus protecting the chip and wires from atmosphere, while the molding compound extends to a heat spreader portion, leaving other portions of the heat spreader exposed to atmosphere. A plurality of solder balls are included on the bottom side of the PCB and are used as signal input and output terminals of the package. The BGA package easily dissipates heat during the operation of the package, improving the operational reliability of the package.

Abstract: A method for reproducing a PCB strip for semiconductor packages, wherein a poor quality PCB unit included in the PCB strip is replaced with a normal quality one, thereby achieving a reduction in the amount of package materials used and an improvement in the process efficiency. The invention also provides a method for fabricating semiconductor packages using the PCB strip reproduction method. A desired portion of a poor quality PCB unit included in a PCB strip is cut out in such a manner that a cutting opening having a peripheral edge extending along the singulation line of the poor quality PCB unit or along a region defined between the singulation line and anti-bending slots of the poor quality PCB unit. In the cutting opening, a separate good quality PCB unit member having the same shape and size as the cutting opening is then fitted. Thus, it is possible to simply and efficiently replace PCB units determined to be of poor quality with separate good quality PCB unit members, respectively.

Abstract: A solder ball land metal structure of a ball grid array semiconductor package capable of obtaining a maximum contact area between a solder ball land metal element and a solder ball fused on the land metal element. A solder mask defined type land metal structure according to the present invention has a single etching hole at the central portion thereof or a plurality of etching holes at the outer portion thereof in order to obtain an increased contact area for a solder ball. Each etching hole extends from the upper surface of the land metal element to the upper surface of the BT substrate throughout the land metal element or extends from the upper surface of the land metal element to a depth corresponding to about half the thickness of the land metal element. Each etching hole serves as a locking hole for fixing the fused solder ball. Thus, it is effectively prevent the solder ball from being separated from the land metal element.

Abstract: The invention relates to a grid array type lead frame having a plurality of leads classified into groups by length forming a lead end grid array semiconductor package. The leads extend to respective lead ends, in each of which at least one different plane direction-converting lead part and/or at least one identical plane direction-converting lead part is formed by at least one bending part, whereby the lead ends are distributed in a grid array. The invention includes a lead end grid array semiconductor package employing the grid array type lead frame, which is as small as or similar to that of semiconductor chip in area while the lead ends are arrayed on one plane, farther distant way from neighboring ones but in a higher number per area, in such a manner that they form a grid array.

Abstract: A mounting for a semiconductor integrated circuit device, such as a charge coupled device ("CCD") or an erasable programmable read only memory device ("EPROM"), includes an insulating substrate having an aperture between its first and second surfaces. A first surface of the integrated circuit device is placed adjacent to and facing the first surface of the substrate. Light sensitive circuitry on the first surface of the integrated circuit device is aligned with the aperture. Solder bumps on the periphery of the first surface of the integrated circuit are electrically connected to corresponding conductive metallizations on the first surface of the substrate. A aperture cover transparent to light is affixed to the second surface of the substrate and extends over the aperture, so that light may be transmitted through the aperture cover and aperture to the light sensitive circuitry on the first surface of the integrated circuit device. The substrate may be a printed circuit board.