Abstract: A method includes setting lead eye boxes and lead eye points on a gate and a support bar of a lead frame, before clamping the lead frame, and determining whether or not the lead frame is seated in an exact first position. The lead eye boxes and the lead eye points are again set on the gate and the support bar, after clamping the lead frame, and it is redetermined whether or not the lead frame is seated in the exact first position. The positions of leads of the lead frame are captured and memorized. Die eye boxes and die eye points are set on specific patterns of a die and it is determined whether or not the die is mounted in an exact second position.

Abstract: A grid array assembly is provided employing a thin copper or steel carrier frame having apertures extending longitudinally of the frame. A series of semi-flexible substrate printed circuit boards are mounted in seriatim to peripheral edges of the apertures, the circuit boards including bonding pads and metallization on a first surface and conductive vias in the circuit boards extending to a second opposite surface containing a contact pad array. The carrier strip with the mounted circuit boards are passed to a station where an IC die is mounted on the board first surface, wire bonds are placed from the die to the bonding pads and the assembly encapsulated using a portion of the carrier strip as a mold gate to form a package body. Subsequently each grid array assembly is singulated from the carrier strip.

Abstract: A method of forming an encapsulated integrated circuit package includes forming a large number of traces spaced a significant distance from the integrated circuit. Intermediate bonding pads are formed between the integrated circuit and the traces. Bond pads of the integrated circuit are electrically connected to corresponding traces by corresponding long wires, which are intermediately bonded to the intermediate bonding pads. Since the long wires are intermediately bonded to intermediate bonding pads and extend along the surface of the substrate, the long wires are not susceptible to wire sweep during the encapsulation process used to form the package body.

Abstract: A method of making an integrated circuit package is disclosed. A conductive first adhesive is applied onto a leadframe pad of a leadframe. A conductive second adhesive is applied on an input portion of the leadframe, such as a leadframe member that is integral with inner portions of input leadfingers. An integrated circuit die, such as a power MOSFET, is placed on the first adhesive on the leadframe pad. A conductive third adhesive is applied onto a surface of the integrated circuit die opposite the leadframe pad. A conductive strap is placed on the third adhesive on the integrated circuit die and on the second adhesive on the leadframe. The first, second and third adhesives are then simultaneously cured so that the integrated circuit die is permanently attached to the leadframe pad, and the conductive strap is permanently attached to the die and the leadframe member.

Abstract: Package embodiments for integrated circuits or other electronic devices are disclosed, along with methods of making and interconnecting the packages. The packages include a package body formed of molded encapsulant. Leads extend from a first end that is embedded at a lower surface of the package body second end that is outside the package body. The leads are bent up the sides of the package and over the top surface of the package. The packages have mounting keys so that a plurality of packages may be precisely stacked one on top of the other. Abutting leads of the stacked packages may be electrically interconnected. The packages also may be placed next to each other so that their leads abut and may be electrically interconnected.

Abstract: In the manufacture of semiconductor packages having molded plastic bodies, the plating of all of the surfaces of the molding tool that comes into contact with the molten resin during molding with a nodular thin dense chromium (“NTDC”) coating prevents the surfaces from adhering to the package body and ensures good package release, without formation of cracks or craters in the package body. This, in turn, permits the amount of both release agents and adhesion promoters used in the molding compound to be substantially reduced, or eliminated altogether, thereby resulting in a package body having improved strength and adhesion with the components of the package, and hence, an improved resistance of the package body to the propagation of cracks and its subsequent penetration by moisture.

Abstract: A method includes identifying and determining a position of a scribe grid on a front-side surface of a wafer with a camera. Based on this information, a laser is fired to form an alignment mark on the back-side surface of the wafer. Advantageously, the alignment mark is positioned with respect to the scribe grid to within tight tolerance. The wafer is then cut from the backside surface using the alignment mark as a reference. Of importance, the wafer is cut from the back-side surface thus protecting the front-side surface of the wafer. Of further importance, the wafer is precisely cut such that the scribe line is not fabricated with the extra large width of scribe lines of conventional wafers designed to be cut from the back-side surface.

Abstract: A thin, stackable semiconductor package having improved electrical and heat dissipating performance comprises a semiconductor chip having an integrated circuit and a plurality of input/output pads on a surface thereof. A lead frame having a plurality of inner leads with upper and a lower surfaces has one of those surfaces bonded to a surface of the chip with a bonding agent. The leads each has a projection formed on at least one of the upper and lower surfaces at a distal end portion of the lead. Each of the leads is electrically connected to an associated input/output pad of the chip through a wire bonding process using electrically conductive wires, or by a ball bonding process using electrically conductive balls. Alternatively, the leads may be directly bonded to the input/output pads of the chip by a TAB bonding process. An encapsulated portion envelops the semiconductor chip and the leads while exposing the projections of the leads to the atmosphere outside the encapsulated portion.

Abstract: A method for forming a metal wiring pattern of a semiconductor device. A metal film is first deposited on a semiconductor substrate, then a photoresist pattern is formed on the metal film. The metal film is etched using the photoresist pattern as a mask, then a portion of the photoresist pattern is removed through an under-ashing process. Thereby, the photoresist pattern does not harden and is readily removable. Next, polymer impurity layer formed during the etching act is removed through a chemical wet cleaning process.

Abstract: A wafer-level method for mass production of surface-mounting, chip-size (“CS”) ball grid array (“BGA”), land grid array (“LGA”), and lead-less chip carrier (“LCC”) semiconductor packages includes the wire-bond or flip-chip attachment of ceramic substrates to the active surface of corresponding chips while they are still integral to a semiconductor wafer, thereby reducing manufacturing costs of the packages relative to that of individually packaged chips. The substrates have a thermal coefficient of expansion (TCE) closely matching that of the underlying chip.

Abstract: Packages for an integrated circuit device and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, leads, bond wires, and an encapsulant. The lower surfaces of the die pad and leads are provided with a stepped profile by an etching step that etches partially through the thickness of a peripheral portion of the die pad, and also etches partially through the thickness of portions of the leads. Encapsulant material fills in beneath the recessed, substantially horizontal surfaces of the die pad and leads formed by the above-described etching step, and thereby prevents the die pad and leads from being pulled vertically from the package body. Other portions of the die pad and leads are exposed at the lower surface of the package for connecting the package externally. A metal leadframe for making an encapsulated package includes an outer frame. A die pad is within and connected to the frame.

Abstract: A package for an integrated circuit device having an optical cell is disclosed. A method of making the package also is disclosed. The package includes a base of molded encapsulant material. A metal leadframe is embedded in the plastic base at the upper surface of the base. Encapsulant material covers the lower and side surfaces of the die pad and the leads of the leadframe, but does not cover the upper surfaces of the die pad and leads. The side surfaces of the die pad and leads have locking features for engaging the encapsulant material. An optical integrated circuit device is attached to the exposed surface of the die pad. An adhesive bead is applied around the optical device on the exposed upper surface of the leads. An optically clear cover is placed on and, in some embodiments, pressed into the still-viscous adhesive bead. When hardened, the bead supports the cover above the optical device.

Abstract: A PCB having oval solder ball lands, and a BGA semiconductor package produced using such a PCB, are disclosed. The PCB has a plurality of conductive traces forming circuit patterns on at least one of an upper and a lower surface of a resin substrate. A plurality of solder ball lands are formed on the lower surface of the substrate and are electrically connected to respective upper surface conductive traces. At least a portion of the solder ball lands have an oval shape and a major axis. The oval solder ball lands are oriented such that their major axes are either radially directed relative to a center of the substrate, perpendicularly directed relative to a side edge of the substrate, or both radially and perpendicularly directed relative the center and a side edge of the substrate, respectively.

Abstract: Image sensor packages are fabricated simultaneously to minimize the cost associated with each individual image sensor package. To fabricate the image sensor packages, windows are molded in molding compound to form a molded window array. A substrate includes a plurality of individual substrates integrally connected together in an array format. Image sensors are attached and electrically connected to corresponding individual substrates. An adhesive layer attaches the molded window array to the substrate. The substrate and attached molded window array are singulated into a plurality of individual image sensor packages.

Abstract: The present invention includes a package for housing an integrated circuit device. The present invention also includes leadframes and methods for making such packages. The package includes an integrated circuit device on a metal die pad. A metal ring is between the die pad and leads and surrounds the die pad. The ring is connected to the die pad by a nonconductive tape. Encapsulant material covers the entire structure. The ring is connected to a lead identified for connection to an external power voltage supply. The ring in turn is connected to a power voltage input pad on the integrated circuit device. The die pad floats, or is connected to a lead that is connected to an external ground voltage. The package is made from a leadframe that has a die pad, a metal ring between the die pad and radiating leads, and a nonconductive tape that connects the ring to the die pad. In one embodiment, the leadframe and package also include a bypass or decoupling capacitor attached between the die pad and the ring.

Abstract: A method of forming a trench for semiconductor device isolation includes the steps of making a trench at a device isolation area of a silicon wafer overlaid with a pad oxide and a nitride through photolithography and etching, forming a liner oxide at an inner wall of the trench, filling the trench through depositing an insulating layer onto the entire surface of the silicon wafer, densifying the insulating layer, and planarizing the densified insulating layer such that the insulating layer is left only at the inside of the trench.

Abstract: A package includes a substrate mechanically supporting circuitry. A conductive cover (e.g., a metal sheet) is over the circuitry so that the circuitry is exposed below an opening in the conductive cover. A bent down corner of the conductive cover is inserted into a hole in the substrate. A solder ball is placed on the other end of the hole. During a subsequent heating, the solder ball is drawn up through the hole. When cooled, the conductive material grasps onto the tip of the bent down corner, thereby establishing a good connection between the conductive cover and the newly formed conductive via. As a finger approaches the circuitry (e.g., a fingerprint detection circuit), the finger first discharges electrostatic charge into the cover, not into the circuit, thereby protecting the circuit. In another package, the cover is composed of a highly resistive material, to slowly dissipate the electrostatic charge.

Abstract: A printed circuit board for BGA semiconductor packages has structure for effectively grounding the PCB to a grounded mold during molding of the package, thus preventing any accumulation of electrostatic charge on the package, and hence, any damage to the semiconductor chips, bonding wires or conductive traces in the packages caused by a rapid discharge of such an accumulated charge. The grounding means may comprise a flat grounding pad, a raised grounding boss, and/or a plated-through, grounding tooling hole on the board. The grounding pad or boss is electrically connected to a ground via hole and/or a ground trace on the board, and is located outside of a package separation line formed on a surface of the PCB. The grounding tooling hole is internally plated with a conductive metal layer to make electrical contact with conductive tooling pins that extend between the molds.

Abstract: A plurality of integrated circuit chip (IC chip) packages are fabricated simultaneously from a single insulating substrate having sections. In each section, an IC chip is attached. Bonding pads on the IC chip are electrically connected to first metallizations on a substrate first surface. The first metallizations, IC chip including bonding pads and first substrate surface are then encapsulated. Interconnection balls or pads are formed at substrate bonding locations on a substrate second surface, the interconnection pads or balls being electrically connected to corresponding first metallizations. The substrate and encapsulant are then cut along the periphery of each section to form the plurality of IC chip packages.

Abstract: A method of molding BGA semiconductor packages comprises grounding a PCB in the package to a grounded mold during the process of molding the package, thus preventing an accumulation of electrostatic charge on the components of the BGA package, thereby preventing any damage to the semiconductor chips, bonding wires or conductive traces in the package resulting from a sudden discharge of such an accumulated charge. The means for grounding the PCB may include grounding projections on one of the molds, and/or may comprise grounding pads, grounding bosses, or grounding tooling holes in the PCB. The grounding projections on the mold are positioned on opposite sides of a runner in the mold. The grounding pads or bosses are electrically connected to a ground via hole and a ground trace, and, in one embodiment are positioned on the bottom surface of the PCB outside of a package separation line.