Abstract: A noise cancellation system for a noise cancellation enabled audio device comprises a first noise filter and a second noise filter, each being designed to process a noise signal, a combiner and an adaptation engine. The first noise filter has a first fixed frequency response matched to a high leakage condition of the audio device. The second noise filter has a second fixed frequency response matched to a low leakage condition of the audio device. The combiner is configured to provide a compensation signal based on a combination of an output of the first noise filter amplified with a first adjustable gain factor and an output of the second noise filter amplified with a second adjustable gain factor. The adaptation engine is configured to estimate a leakage condition of the audio device based on an error noise signal and to adjust at least one of the first and the second adjustable gain factors based on the estimated leakage condition.

Abstract: A circuit arrangement for an optical monitoring system comprises a driver circuit configured to generate at least one driving signal for driving a light source and a detector terminal for receiving a detector current. The circuit arrangement further comprises a current source configured and arranged to generate at the detector terminal a reduction current. The reduction current has an amplitude which is given by a base value whenever none of the least one driving signal assumes a value suitable for activating the light source and by a sum of the base value and a reduction value otherwise. The circuit arrangement also comprises a processing unit configured to generate an output signal depending on a combination of the detector current and the reduction current.

Abstract: A sensor arrangement (10) comprises a capacitive sensor (11) with a first electrode line (12), a second electrode line (16) and a third electrode line (20) and a sensitive layer (30) arranged at the first, the second and the third electrode line (12, 16, 20). The sensor arrangement (10) comprises a readout circuit (50) that comprises a capacitance-to-digital converter (51), is coupled to the first, the second and the third electrode line (12, 16, 20) and is configured to generate a first measurement signal (S1) using the first and the second electrode line (12, 16) and a second measurement signal (S2) using at least the third electrode line (20).

Abstract: A pumping structure comprises at least two membranes, at least two actuation chambers, one evaluation chamber comprising an opening to the outside of the pumping structure, and at least three electrodes. Each membrane is arranged between two electrodes in a vertical direction which is perpendicular to the main plane of extension of the pumping structure, each actuation chamber is arranged between one of the membranes and one of the electrodes in vertical direction, and each actuation chamber is connected to the evaluation chamber via a channel. Furthermore, a particle detector and a method for pumping are provided.

Abstract: A multi-level capacitive digital-to-analog converter, comprises at least one capacitor switch circuit (100) including a differential operational amplifier (130) having a first input node (E130a) and a second input node (E130b). A first current path (101) is coupled to a first reference input terminal (E100a) to apply a first reference potential (RefP) and the second current path (102) is coupled to a second reference input terminal (E100b) to apply a second reference potential (RefN). The at least one capacitor switch circuit (100) comprises a first controllable switch (111) being arranged between the second input node (E130a) of the differential operational amplifier (130) and the first current path (101). The at least one capacitor switch circuit (100) comprises a second controllable switch (112) being arranged between the first input node (E130a) of the differential operational amplifier (130) and the second current path (102).

Abstract: A fluorescence lifetime sensor module comprises an opaque housing having a first chamber and a second chamber which are separated by a light barrier. An optical emitter is arranged in the first chamber and configured to emit through a first aperture. Emission of pulses of light of a specified wavelength is arranged to optically excite a fluorescent probe to be positioned in front of the sensor module. A detector is arranged in the second chamber and configured to detect through a second aperture received photons from the fluorescent probe. A measurement block is configured to determine respective difference values representative of an arrival time of one of the received photons with respect to the emission pulses. A histogram block is configured to accumulate the difference values in a histogram.

Abstract: An assembly line in-situ calibration arrangement, optical sensor arrangement and a method for calibration of an optical sensor arrangement are presented. A calibration arrangement comprises a calibration head comprising at least one calibrated light source located behind an aperture in a housing and being electrically connected to a power terminal. A power source is connected to the power terminal, the power source comprising a switching unit electrically connected to the at least one light source. An interface unit is connected to the switching unit by means of an interface connection, wherein the interface unit is arranged to control the switching unit. A control unit is connected to the interface unit, wherein the control unit is arranged to drive the interface unit such that the at least one light source is switched to emit a calibration pulse sequence to be received by the optical sensor arrangement to be placed with respect of the aperture.

Abstract: An optical package is proposed comprising a carrier, an optoelectronic component, an aspheric lens, and a reflective layer. The carrier comprises electrical interconnections and the optoelectric component is arranged for emitting and/or detecting electromagnetic radiation in a specified wavelength range. Furthermore, the optoelectric component is mounted on the carrier or integrated into the carrier and electrically connected to the electric interconnections. The aspheric lens has an upper surface, a lateral surface, and a bottom surface and the bottom surface is arranged on or near the optoelectric component. The aspheric lens comprises a material which is at least transparent in the specified wavelength range. The reflective layer comprises a reflective material, wherein the reflective layer at least partly covers the lateral surface of the aspheric lens, and wherein the reflective material is at least partly reflective in the specified wavelength range.

Abstract: The oscillator circuit comprises first and second integrator units with a first capacitor charged at a first integration node and a second capacitor charged at a second integration node. A comparator unit is arranged between a first switching unit, which is connected to the integration nodes and to a reference signal (VREF), and a second switching unit. The comparator unit compares a signal from the first or second integration node with the reference signal. The second switching unit is connected to a logic unit configured to provide signals controlling the first integrator unit, the second integrator unit, the first switching unit and the second switching unit, so that a periodic operation is generated by alternatingly activating the first integrator unit and the second integrator unit.

Abstract: The PLL circuit comprises a phase/frequency detector (302), a loop filter (304, 306), a VCO (308) and a feedback loop (320). The VCO can be electrically disconnected from the PLL and comprises a programmable trimming circuit (316) and a current-controlled oscillator (318). For calibration the VCO is electrically disconnected from the loop filter and from the feedback loop, a constant reference voltage is applied to the voltage input (IN), a center frequency programming code (L) is applied to the trimming circuit, the center frequency programming code is iteratively adjusted until a desired center frequency is obtained, a gain programming code (K) is applied to the trimming circuit while the adjusted code is still applied, and the gain programming code is iteratively adjusted until a desired gain is obtained. Then the VCO is connected to the PLL, which is then ready for normal operation.

Abstract: A charger control circuit (CC) comprises a first charger terminal (CT1) and a system terminal (ST) and is configured to assign a voltage applied at the first charger terminal (CT1) to one of at least three voltage ranges by performing at least one voltage comparison. The charger control circuit (CC) is configured to determine and distinguish, based on the assignment, whether an external charger (EXC1) or a secondary battery (SBAT) is connected to the first charger terminal (CT1). Furthermore, the charger control circuit (CC) is configured to, depending on a predetermined operating state of the first charger terminal (CT1), supply power from the secondary battery (SBAT) or the external charger (EXC1) to a portable electronic device via the system terminal (ST) when the secondary battery (SBAT) or the external charger, respectively, is connected to the first charger terminal (CT1).

Abstract: A sensor arrangement (10) comprises an amplifier (11) having a signal input (12) to receive an input signal (SIN) and a signal output (13) to provide an amplified sensor signal (SOUT) that is an inverted signal with respect to the input signal (SIN). Furthermore, the sensor arrangement (10) comprises a feedback path connecting the signal output (13) to the gnal input (12), wherein the feedback path comprises a series connection of a capacitive sensor (14) and a feedback capacitor (15). A voltage source arrangement (19) of the sensor arrangement (10) is connected to a feedback node (18) between the capacitive sensor (14) and the feedback capacitor (15).

Abstract: An analog-to-digital converter (10) comprises a first and a second sampling capacitor (24, 25), a first integrator (26), a first and a second input switch (31, 32) coupling a first input terminal (11) and a common mode terminal (39) to a first electrode of the first sampling capacitor (24), a third and a fourth input switch (33, 34) coupling a second input terminal (12) and the common mode terminal (39) to a first electrode of the second sampling capacitor (25), a fifth and a sixth input switch (35, 36) coupling a second electrode of the first sampling capacitor (24) to an amplifier common mode terminal (40) and the first integrator input (27), and a seventh and an eighth input switch (37, 38) coupling a second electrode of the second sampling capacitor (25) to the amplifier common mode terminal (40) and the second integrator input (28).

Abstract: An integrator circuit (10) for use in a sigma-delta modulator (1) comprises a differential operational amplifier (130) with a first input node (E130a) and a second input node (E130b). The first input node (E130a) of the differential operational amplifier (130) is connected to a first current path (101) and the second input node (E130b) of the differential operational amplifier (130) is connected to a second current path (102). A first controllable switch (111) is arranged between the second input node (E130b) of the differential operational amplifier (130) and the first current path (101). A second controllable switch (112) is arranged between the first input node (E130a) of the differential operational amplifier (130) and the second current path (102). A third controllable switch (113) is arranged between a reference potential (RP) and the first current path (101). A fourth controllable switch (114) is arranged between the reference potential (RP) and the second current path (102).

Abstract: An output circuit comprises an output terminal (11), a first current mirror (12), a first pass transistor (13) and a first delivering terminal (14) coupled via the first current mirror (12) and the first pass transistor (13) to the output terminal (11).

Abstract: At least one of the pixels of the image sensor is heated using at least one heater, and the temperature of this pixel is thus increased by a larger degree than the temperature of at least a further one of the pixels.

Abstract: In one embodiment an analog-to-digital converter circuit has an input for receiving a first analog signal level and a second analog signal level, a ramp generator adapted to provide a ramp signal, a comparison unit coupled to the input and the ramp generator, a control unit coupled to the comparison unit the control unit having a counter, the control unit being prepared to enable the counter as a function of a comparison of the ramp signal with the first analog signal level and the second analog signal level, and an output for providing an output digital value as a function of a relationship between the first analog signal level and the second analog signal level. Therein the ramp signal has at least one linearly rising and at least one linearly falling portion and an adjustable shift at a reversal point between the rising and the falling portion of the ramp signal, the shift depending on the number of rising and falling portions of the ramp signal.

Abstract: The photodetector device comprises a substrate (1) of semiconductor material, a sensor region (2) in the substrate, a plurality of grid elements (4) arranged at a distance (d) from one another above the sensor region, the grid elements having a refractive index, a region of lower refractive index (3), the grid elements being arranged on the region of lower refractive index, and a further region of lower refractive index (5) covering the grid elements.

Abstract: A sensor arrangement for determining time-of-flight comprises an emitter configured to periodically emit pulses of electromagnetic radiation depending on a first clock signal, a photonic demodulator configured to detect electromagnetic radiation during detection intervals comprising first and second intervals and a processing circuit. A timing of the detection intervals is defined by a second clock signal having a phase difference with respect to the first clock signal. The demodulator is configured to generate demodulator signals depending on energy of the radiation detected during at least one of the first intervals and at least one of the second intervals, respectively. The processing circuit is configured to adapt the phase difference based on the demodulator signals and to generate an output signal indicative of the time-of-flight based on the phase difference.

Abstract: The integrated smoke detection device comprises a carrier (1), a light source (2) arranged on or above the carrier, a light receiver (3) arranged on or above the carrier at a distance from the light source, and a polarizing member (7) arranged on or above the carrier, the light source emitting radiation (a, b) into the polarizing member. The polarizing member is configured to have a boundary surface (11) that linearly polarizes a reflected portion (d) of the radiation emitted by the light source, and an exit surface (12) that allows the reflected portion (d) to exit the polarizing member.