Abstract: A circuit arrangement for an optical monitoring system comprises a driver circuit configured to generate at least one driving signal for driving a light source and a detector terminal for receiving a detector current. The circuit arrangement further comprises a current source configured and arranged to generate at the detector terminal a reduction current. The reduction current has an amplitude which is given by a base value whenever none of the least one driving signal assumes a value suitable for activating the light source and by a sum of the base value and a reduction value otherwise. The circuit arrangement also comprises a processing unit configured to generate an output signal depending on a combination of the detector current and the reduction current.

Abstract: A pumping structure comprises at least two membranes, at least two actuation chambers, one evaluation chamber comprising an opening to the outside of the pumping structure, and at least three electrodes. Each membrane is arranged between two electrodes in a vertical direction which is perpendicular to the main plane of extension of the pumping structure, each actuation chamber is arranged between one of the membranes and one of the electrodes in vertical direction, and each actuation chamber is connected to the evaluation chamber via a channel. Furthermore, a particle detector and a method for pumping are provided.

Abstract: The PLL circuit comprises a phase/frequency detector (302), a loop filter (304, 306), a VCO (308) and a feedback loop (320). The VCO can be electrically disconnected from the PLL and comprises a programmable trimming circuit (316) and a current-controlled oscillator (318). For calibration the VCO is electrically disconnected from the loop filter and from the feedback loop, a constant reference voltage is applied to the voltage input (IN), a center frequency programming code (L) is applied to the trimming circuit, the center frequency programming code is iteratively adjusted until a desired center frequency is obtained, a gain programming code (K) is applied to the trimming circuit while the adjusted code is still applied, and the gain programming code is iteratively adjusted until a desired gain is obtained. Then the VCO is connected to the PLL, which is then ready for normal operation.

Abstract: The oscillator circuit comprises first and second integrator units with a first capacitor charged at a first integration node and a second capacitor charged at a second integration node. A comparator unit is arranged between a first switching unit, which is connected to the integration nodes and to a reference signal (VREF), and a second switching unit. The comparator unit compares a signal from the first or second integration node with the reference signal. The second switching unit is connected to a logic unit configured to provide signals controlling the first integrator unit, the second integrator unit, the first switching unit and the second switching unit, so that a periodic operation is generated by alternatingly activating the first integrator unit and the second integrator unit.

Abstract: An integrator circuit (10) for use in a sigma-delta modulator (1) comprises a differential operational amplifier (130) with a first input node (E130a) and a second input node (E130b). The first input node (E130a) of the differential operational amplifier (130) is connected to a first current path (101) and the second input node (E130b) of the differential operational amplifier (130) is connected to a second current path (102). A first controllable switch (111) is arranged between the second input node (E130b) of the differential operational amplifier (130) and the first current path (101). A second controllable switch (112) is arranged between the first input node (E130a) of the differential operational amplifier (130) and the second current path (102). A third controllable switch (113) is arranged between a reference potential (RP) and the first current path (101). A fourth controllable switch (114) is arranged between the reference potential (RP) and the second current path (102).

Abstract: An analog-to-digital converter (10) comprises a first and a second sampling capacitor (24, 25), a first integrator (26), a first and a second input switch (31, 32) coupling a first input terminal (11) and a common mode terminal (39) to a first electrode of the first sampling capacitor (24), a third and a fourth input switch (33, 34) coupling a second input terminal (12) and the common mode terminal (39) to a first electrode of the second sampling capacitor (25), a fifth and a sixth input switch (35, 36) coupling a second electrode of the first sampling capacitor (24) to an amplifier common mode terminal (40) and the first integrator input (27), and a seventh and an eighth input switch (37, 38) coupling a second electrode of the second sampling capacitor (25) to the amplifier common mode terminal (40) and the second integrator input (28).

Abstract: A sensor arrangement (10) comprises an amplifier (11) having a signal input (12) to receive an input signal (SIN) and a signal output (13) to provide an amplified sensor signal (SOUT) that is an inverted signal with respect to the input signal (SIN). Furthermore, the sensor arrangement (10) comprises a feedback path connecting the signal output (13) to the gnal input (12), wherein the feedback path comprises a series connection of a capacitive sensor (14) and a feedback capacitor (15). A voltage source arrangement (19) of the sensor arrangement (10) is connected to a feedback node (18) between the capacitive sensor (14) and the feedback capacitor (15).

Abstract: A charger control circuit (CC) comprises a first charger terminal (CT1) and a system terminal (ST) and is configured to assign a voltage applied at the first charger terminal (CT1) to one of at least three voltage ranges by performing at least one voltage comparison. The charger control circuit (CC) is configured to determine and distinguish, based on the assignment, whether an external charger (EXC1) or a secondary battery (SBAT) is connected to the first charger terminal (CT1). Furthermore, the charger control circuit (CC) is configured to, depending on a predetermined operating state of the first charger terminal (CT1), supply power from the secondary battery (SBAT) or the external charger (EXC1) to a portable electronic device via the system terminal (ST) when the secondary battery (SBAT) or the external charger, respectively, is connected to the first charger terminal (CT1).

Abstract: An output circuit comprises an output terminal (11), a first current mirror (12), a first pass transistor (13) and a first delivering terminal (14) coupled via the first current mirror (12) and the first pass transistor (13) to the output terminal (11).

Abstract: At least one of the pixels of the image sensor is heated using at least one heater, and the temperature of this pixel is thus increased by a larger degree than the temperature of at least a further one of the pixels.

Abstract: In one embodiment an analog-to-digital converter circuit has an input for receiving a first analog signal level and a second analog signal level, a ramp generator adapted to provide a ramp signal, a comparison unit coupled to the input and the ramp generator, a control unit coupled to the comparison unit the control unit having a counter, the control unit being prepared to enable the counter as a function of a comparison of the ramp signal with the first analog signal level and the second analog signal level, and an output for providing an output digital value as a function of a relationship between the first analog signal level and the second analog signal level. Therein the ramp signal has at least one linearly rising and at least one linearly falling portion and an adjustable shift at a reversal point between the rising and the falling portion of the ramp signal, the shift depending on the number of rising and falling portions of the ramp signal.

Abstract: A sensor arrangement for determining time-of-flight comprises an emitter configured to periodically emit pulses of electromagnetic radiation depending on a first clock signal, a photonic demodulator configured to detect electromagnetic radiation during detection intervals comprising first and second intervals and a processing circuit. A timing of the detection intervals is defined by a second clock signal having a phase difference with respect to the first clock signal. The demodulator is configured to generate demodulator signals depending on energy of the radiation detected during at least one of the first intervals and at least one of the second intervals, respectively. The processing circuit is configured to adapt the phase difference based on the demodulator signals and to generate an output signal indicative of the time-of-flight based on the phase difference.

Abstract: The photodetector device comprises a substrate (1) of semiconductor material, a sensor region (2) in the substrate, a plurality of grid elements (4) arranged at a distance (d) from one another above the sensor region, the grid elements having a refractive index, a region of lower refractive index (3), the grid elements being arranged on the region of lower refractive index, and a further region of lower refractive index (5) covering the grid elements.

Abstract: A portable environment sensing device is described which comprises at least one time-of-flight sensor capable of detecting the distances from the time-of-flight sensor to at least two features within the field of view of the time-of-flight sensor simultaneously. The portable environment sensing device further comprises a processing unit capable of converting the at least two measured distances into at least two different distance signals, where each distance signal is correlated with the corresponding measured distance, and an output interface providing the at least two distance signals to a user simultaneously.

Abstract: The integrated smoke detection device comprises a carrier (1), a light source (2) arranged on or above the carrier, a light receiver (3) arranged on or above the carrier at a distance from the light source, and a polarizing member (7) arranged on or above the carrier, the light source emitting radiation (a, b) into the polarizing member. The polarizing member is configured to have a boundary surface (11) that linearly polarizes a reflected portion (d) of the radiation emitted by the light source, and an exit surface (12) that allows the reflected portion (d) to exit the polarizing member.

Abstract: In an embodiment an oscillator circuit comprises a first integrator-comparator unit, a second integrator-comparator unit, and a logic circuit. The first integrator-comparator unit is prepared to provide a first signal as a function of a first integration of a first charging current and a subsequent comparison of a first integration signal resulting from the first integration with a reference signal. The second integrator-comparator unit is prepared to provide a third signal as a function of a second integration of a second charging current and a subsequent comparison of a second integration signal resulting from the second integration with the reference signal. The logic circuit is adapted to provide a clock signal, a first and a second measurement signal for respectively controlling the first and the second integrator-comparator unit.

Abstract: A method for transmission path noise control using an audio headset and a sending device comprises generating microphone signals by a first and a second microphone of the headset based on detected sound including desired audio information and noise. An encoded signal is generated on a first line of a data cable by means of the headset by encoding input signals depending on the microphone signals. The method comprises transmitting the encoded signal from the headset to the sending device via the first, reconstructing the input signals by decoding the encoded signal by the sending device, generating by the sending device a clean signal by applying a first noise control algorithm to the reconstructed first and second input signal and sending a signal depending on the clean signal to a communication network.

Abstract: A time-to-digital converter system has at least one time-to-digital converter comprising an oscillator, a counter being driven by the oscillator, an evaluation block connected to the counter and configured for determining a time difference associated with a start signal and a stop signal, and a histogram block with a number of bins for recording entries associated with the time difference. The system can be calibrated by operating or preparing to operate the time-to-digital converter system with a measurement clock signal defining a measurement interval, providing a calibration clock signal having a frequency higher than the measurement clock signal by a predefined ratio, using a selected clock edge of the calibration clock signal as the start signal and a subsequent clock edge of the calibration clock signal as the stop signal. The evaluation block determines a calibration time difference based on the respective clock edges of the calibration clock signal used as the start signal and the stop signal.

Abstract: A method of producing an optical sensor at wafer-level, comprising the steps of providing a wafer having a main top surface and a main back surface and arrange at or near the top surface of the wafer at least one first integrated circuit having at least one light sensitive component. Furthermore, providing in the wafer at least one through-substrate via for electrically contacting the top surface and back surface and forming a first mold structure by wafer-level molding a first mold material over the top surface of the wafer, such that the first mold structure at least partly encloses the first integrated circuit. Finally, forming a second mold structure by wafer-level molding a second mold material over the first mold structure, such that the second mold structure at least partly encloses the first mold structure.

Abstract: An optical sensor arrangement has an integrator, a photodiode for providing a current corresponding to a first polarity, a comparator coupled to the integrator for comparing a voltage with a threshold voltage to provide a comparison output, a reference charge circuit and a control unit. The reference charge circuit is coupled to the integrator for selectively providing first charge packages of a first size or second charge packages of a second size. The control unit is configured to control operation in a calibration phase, in an integration phase and in a residual measurement phase. During the calibration phase, the reference charge circuit provides one of the first charge packages and one or more of the second charge packages to the integrator until the comparison output changes. A reference number is determined corresponding to a number of the second charge packages provided.