Abstract: A semiconductor substrate is provided with a through-substrate via comprising a metallization and an opening. A solder ball is placed on the opening. A reflow of the solder ball is performed in such a way that the solder ball closes the through-substrate via and leaves a void in the through-substrate via.

Abstract: A portable object (10) comprises an integrated circuit (11), a first pad (12) that is mechanically and electrically connected to the integrated circuit (11) and a second pad (13) that is mechanically and electrically connected to the integrated circuit (11). The portable object (10) is designed for data transfer by capacitive coupling of the first pad (12) to a first conducting line (33) and of the second pad (13) to a second conducting line (34), when the portable object (10) is brought in vicinity to the first and the second conducting line (33, 34).

Abstract: The method comprises the steps of applying a layer of a negative photoresist on a bottom layer, providing the layer of the negative photoresist with a pattern arranged in a border zone of the resist structure to be produced, irradiating a surface area of the layer of the negative photoresist according to the resist structure to be produced, and removing the layer of the negative photoresist outside the irradiated surface area. The pattern is produced in such a manner that it comprises a dimension that is smaller than a minimal resolution of the irradiation. The pattern may especially be designed as a sub-resolution assist feature.

Abstract: A wiring (3) comprising electrical conductors (4, 5, 6, 7) is formed in a dielectric layer (2) on or above a semiconductor substrate (1), an opening is formed in the dielectric layer to uncover a contact pad (8), which is formed by one of the conductors, and a further opening is formed in the dielectric layer to uncover an area of a further conductor (5), separate from the contact pad. The further opening is filled with an electrically conductive material (9), and the dielectric layer is thinned from a side opposite the substrate, so that the electrically conductive material protrudes from the dielectric layer.

Abstract: A delta-sigma modulator (10) comprises a modulator loop (11) and a code generator (12). The modulator loop (11) comprises a loop filter (18). The code generator (12) is configured to generate a generator signal (BS) that is realized as an extended Barker code. The code generator (12) comprises a generator output (23) that is coupled to the loop filter (18).

Abstract: A connector for capacitive coupling of a first communicator and a second communicator of a communication system has a first, a second, a third and a fourth electrode, all of which are electrically conductive. The first and third electrodes are designed to be coupled to the first communicator. The second and fourth electrodes are designed to be coupled to the second communicator. The electrodes are designed to constitute capacitive couplings. Additionally, the first and the second electrode are designed to induce an attractive force between themselves by using a magnetic interaction. Analogously, the third and the fourth electrode are designed to induce an attractive force between themselves by using a magnetic interaction.

Abstract: The semiconductor device comprises a substrate (1) of semiconductor material, a dielectric layer (2) above the substrate, a waveguide (3) arranged in the dielectric layer, and a mirror region (4) arranged on a surface of a mirror support (5) integrated on the substrate. A mirror is thus formed facing the waveguide. The surface of the mirror support and hence the mirror are inclined with respect to the waveguide.

Abstract: A voltage reference source includes a source block, a first resistor having a first terminal coupled to a first terminal of the source block, a reference output for providing a reference voltage, and a first and a second mirror transistor forming a first current mirror. The first mirror transistor couples a second terminal of the source block to a supply voltage terminal and the second mirror transistor couples the reference output to the supply voltage terminal. A series connection of a second resistor and a diode is arranged between the reference output and the first terminal of the first resistor. A mirror current flows through the second mirror transistor and the series connection to the first terminal of the first resistor.

Abstract: The semiconductor drift device comprises a deep well of a first type of electrical conductivity provided for a drift region in a substrate of semiconductor material, a drain region of the first type of conductivity at the surface of the substrate, a plurality of source regions of the first type of conductivity in shallow wells of the first type of conductivity at the periphery of the deep well of the first type, and a deep well or a plurality of deep wells of an opposite second type of electrical conductivity provided for a plurality of gate regions at the periphery of the deep well of the first type. The gate regions are formed by shallow wells of the second type of electrical conductivity, which are arranged in the deep well of the second type between the shallow wells of the first type.

Abstract: A transceiver circuit with a front-end and a back-end is provided. The front-end has terminals for coupling to a first and a second capacitor and tunable resistors coupled between the terminals and a reference terminal. The front-end is configured to receive receiver signals at the terminals utilizing a first setting for the resistors. The front-end is configured to generate a receiver data packet based on the receiver signals. The back-end is configured to check the receiver data packet for errors with respect to a defined tuning data packet. If an error is found, the back-end sets the resistors to a default setting. If no errors are found, the back-end sets the resistors to a second setting.

Abstract: In one embodiment an Inductive buck-boost-converter has an input (In) to which an input voltage (Vin) is supplied, an output (Out) at which an output voltage (Vout) is provided as a function of the input voltage (Vin), an inductor (L) having a first and a second terminal (Lx1, Lx2), a first switch (A) which switchably connects the inductor's (L) first terminal (Lx1) to the input (In), a second switch (B) which switchably connects the inductor's (L) first terminal (Lx1) to a ground potential terminal (10), a third switch (C) which switchably connects the inductor's (L) second terminal (Lx2) to the ground potential terminal (10), a fourth switch (D) which switchably connects the inductor's (L) second terminal (Lx2) to the output (Out), and a control unit (CTL) coupled to respective control inputs of first, second, third and fourth switches (A, B, C, D). Therein the converter is operated in three phases (1, 2, 3) by the control unit (CTL).

Abstract: An optical sensor arrangement (10) comprises a photodiode (11) for providing a sensor current (IPD) and an analog-to-digital converter arrangement (12) which is coupled to the photodiode (11) and determines a digital value of the sensor current (IPD) in a charge balancing operation in a first phase (A) and in another conversion operation in a second phase (B).

Abstract: The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises an annular cavity (18) and a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for three-dimensional integration is offered by this scheme.

Abstract: A driver assembly (100) for a lighting unit (230) comprises a control unit (110). The lighting unit (230) comprises a plurality of strands (240, 250, 260), wherein each strand comprises a series circuit (242, 252, 262) of light-emitting diodes and a current source (243, 253, 263) with a first and a second terminal (246, 256, 266), and wherein the series circuit (242, 252, 262) of diodes is connected between a supply voltage input (231) of the lighting unit (230) and the first terminal of the current source (243, 253, 263) and the second terminal (246, 256, 266) of the current source is connected to a reference potential terminal via a resistor (245, 255, 265).

Abstract: A proximity sensor arrangement comprises an optical barrier being placed between a light emitting device and a photo-detector. The light emitting device, the photo-detector and the optical barrier are covered by a cover. The optical barrier is being designed to block light emitted from the light emitting device to the photo-detector and reflected by the cover by means of specular reflection. Furthermore, the optical barrier is being designed to pass the light emitted from the light emitting device to the photo-detector via the cover and scattered on or above a first surface of the cover facing away from the light emitting device and the photo-detector.

Abstract: In one embodiment, a method for switching an electrical load having at least one capacitive component and one inductive component in a bridge branch of a bridge circuit comprises a charging of the bridge branch to a first voltage (V1) in a forward switching phase (F), a discharging of the capacitive component of the electrical load in a first open switching phase (O1), a charging of the bridge branch to a second voltage (V2) in a reverse switching phase (R), with the second voltage (V2) being polarized inversely from the first voltage (V1), and a negative charging of the capacitive component of the electrical load in a second open switching phase (O2). A bridge circuit is also provided.

Abstract: The high-voltage transistor device comprises a semiconductor substrate (1) with a source region (2) of a first type of electrical conductivity, a body region (3) including a channel region (4) of a second type of electrical conductivity opposite to the first type of conductivity, a drift region (5) of the first type of conductivity, and a drain region (6) of the first type of conductivity extending longitudinally in striplike fashion from the channel region (4) to the drain region (6) and laterally confined by isolation regions (9). The drift region (5) comprises a doping of the first type of conductivity and includes an additional region (8) with a net doping of the second type of conductivity to adjust the electrical properties of the drift region (5). The drift region depth and the additional region depth do not exceed the maximal depth (17) of the isolation regions (9).

Abstract: A circuit for DC-DC conversion with current limitation comprises a DC-DC converter (100) with a coil (110) and a controllable switch (120) that can be switched into a low-impedance and a high-impedance state, and a current limiter (300a, 300b) for generating a control signal (IOC) for controlling the state of the controllable switch in the DC-DC converter (100). The current limiter (300a, 300b) is constructed such that the current (IL) through the coil at which the current limitation takes place is nearly independent of the ratio of the on-times and off-times of the controllable switch in the DC-DC converter (100).

Abstract: The symmetric LDMOS transistor comprises a semiconductor substrate (1), a well (2) of a first type of conductivity in the substrate, and wells (3) of an opposite second type of conductivity. The wells (3) of the second type of conductivity are arranged at a distance from one another. Source/drain regions (4) are arranged in the wells of the second type of conductivity. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) on the gate dielectric. A doped region (10) of the second type of conductivity is arranged between the wells of the second type of conductivity at a distance from the wells. The gate electrode has a gap (9) above the doped region (10), and the gate electrode overlaps regions that are located between the wells (3) of the second type of conductivity and the doped region (10).

Abstract: In an embodiment a shunt driver circuit has a first and a second connection terminal (N1, N2) forming a two-wire interface (N1, N2), the first connection terminal (N1) being prepared to receive a supply power and to provide an output signal (Sout), the second connection terminal (N2) being connected to a reference potential terminal (10), an Operational Transconductance Amplifier, OTA, (11) comprising a first input coupled to the first connection terminal (N1), a second input for receiving a first reference signal (Sref1) and an output (12) for providing a signal (S12) depending on a difference between an input signal on the first input and the first reference signal (Sref1), a capacitor (C1) coupled between the output (12) and the first input of the OTA (11) via the second connection terminal (N2) in a control loop, and a controlled current source (13) coupled between the output (12) of the OTA (11) and the second connection terminal (N2).