Abstract: Analog circuits are often non-linear, and the non-linearities can hurt performance. Designers would trade off power consumption to achieve better linearity. An efficient and effective calibration technique can address the non-linearities and reduce the overall power consumption. A dither signal injected to the analog circuit can be used to expose the non-linear behavior in the digital domain. To detect the non-linearities, a counting approach is applied to isolate non-linearities independent of the input distribution. The approach is superior to and different from other approaches in many ways.

Abstract: In a teeter-totter type MEMS accelerometer, the teeter-totter proof mass and the bottom set of electrodes (i.e., underlying the proof mass) are formed on a device wafer, while the top set of electrodes (i.e., overlying the teeter-totter proof mass) are formed on a circuit wafer that is bonded to the device wafer such that the top set of electrodes overlie the teeter-totter proof mass. The electrodes formed on the circuit wafer may be formed from an upper metallization layer on the circuit wafer, which also may be used to form various electrical connections and/or bond pads.

Abstract: A method of fabricating a super-capacitor provides a substrate, and then adds an electrode and electrolyte template film, having a well for receiving the electrode, to the substrate. The method also adds a second electrolyte to the electrode and electrolyte template.

Abstract: A method is described and in one embodiment includes detecting a transition of a data signal comprising a data packet received at a circuit while the circuit is in a first hysteresis mode; placing the circuit in a second hysteresis mode subsequent to the detecting; and returning the receiver to the first hysteresis mode subsequent to completion of receipt of the data packet to await receipt of a next data packet. In certain embodiments, the first hysteresis mode is a high hysteresis mode and the second hysteresis mode is a standard hysteresis mode. In some embodiments, a level of each of the first and second hysteresis modes is dynamically tunable.

Abstract: Techniques for linearizing a field effect transistor (FET) are provided. In an example, a method can include averaging a voltage at a drain node of the FET and a voltage at a source node of the FET to provide an average voltage, and applying the average voltage to a gate node of the FET.

Abstract: The present disclosure addresses thermal issues in a multi gate finger field-effect transistor (FET) by providing a multi-gate finger FET arrangement where the respective distances between the multiple gate fingers are modulated along the device, such that the distances between the gate fingers in or towards the middle of the device are greater than the distances between the gate fingers at the or towards the edge of the device. By providing the greater distances between gate fingers located in or towards the middle of the device then improved thermal management properties are obtained, and the device as a whole is maintained cooler than would otherwise be the case, with associated improvements in device lifetimes.

Abstract: In a cascaded integrator comb (CIC) filter, a time-varying gain is added before the last integrating stage transforming its sub optimal boxcar impulse response into an FIR filter of arbitrary length. Make the coefficients sparse and taking them from a set of small integers leads to an efficient hardware implementation that does not compromise any of the essential CIC filter characteristics especially the overflow handling. The proposed sparse CIC structure can improve the worst case stop band attenuation by as much as 10 dB while occupying 77% of the chip area and consuming 30% less power compared to a standard a 5th order CIC filter, and reducing the overall bit growth of the filter and the amount of high rate operations. Design examples are given illustrating the advantages and flexibility of the proposed structure.

Abstract: Using various circuits and methods, current can be controlled when a circuit board is plugged into a powered system using two charging paths so that a first current can be supplied between a supply voltage and the load in a first charging path during a first time period and a second current can be supplied between the supply voltage and the load in a second charging path during a second time period.

Abstract: The present disclosure provides systems and methods to provide a constant common mode voltage at the input terminals of a difference amplifier. A difference amplifier can receive an input signal and can deliver an amplified version of the received input signal at an output of the difference amplifier. In a system where a difference amplifier can receive an output of a digital-to-analog converter (DAC), the DAC performance can deteriorate in situations where common mode voltage at the input terminals of the difference amplifier are changing. A difference amplifier including feedback circuitry can provide a constant common mode voltage at the input terminals of the difference amplifier, leading to improved performance in a system where the difference amplifier receives an input signal from a DAC.

Abstract: Conventional user interface for sensing gestures often require physical touching of a sensor pad, or an area filled with sensor pads. These conventional sensor pads take up precious real estate on a compact mobile device, interferes significantly with other components of the mobile device, complicates design, consumes power, and adds costs to the final product. With two or more small capacitive sensing electrodes placed on a mobile device (arbitrarily or with far less restrictions), capacitive sensing can provide a virtual sensor pad as a user interface. By implementing an algorithm which detects for three different conditions, the virtual sensor pad can be used effectively as a user interface modality to detect gestures such as a sliding gesture, drawing gesture, letters, writing, etc. The resulting virtual sensor pad can flexibly change to different desirable locations, and no longer suffers from the limitations of the conventional sensor pad.

Abstract: Circuits and methods for compensating microelectromechanical system (MEMS) gyroscopes for quality factor variations are described. Quality factor variations arise when mechanical losses are introduced in the gyroscope's resonator, for example due to thermoelastic damping or squeeze-film damping, which may hinder the gyroscope's ability to accurately sense angular velocity. Quality factor compensation may be performed by generating a compensation signal having a time decay rate that depends on the quality factor of resonator. In this way, artifacts that may otherwise arise in gyroscope's output are limited. Additionally, or alternatively, quality factor compensation may be performed by controlling the force with which the gyroscope's resonator is driven. This may be achieved, for example, by controlling the average value of the drive signal.

Abstract: A sigma-delta ADC circuit with an analog loop filter circuit can be multiplexed between different inputs by flushing the memory of the analog loop filter integrators and the digital decimation filter and filling it with new data for the current input. However, filling the memory can be slow with respect to the sampling frequency because the information about past history has to be built up before meaningful output data can be generated. Thus, the multiplexing rate between channels using a sigma-delta ADC circuit can be slowed by such memory flushing. A multiplexed sigma-delta ADC circuit is described that can overcome these problems so as to be able to support cycle-by-cycle sampling of multiple channels. These techniques can provide a fast sigma-delta analog-to-digital converter (ADC) circuit that is small in area and that can multiplex over a number of channels dynamically.

Abstract: To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.

Abstract: Systems and methods are disclosed for a noise-shaping successive approximation register (SAR) analog-to-digital-converter (ADC) using Sampled Analog Technology (SAT) filter techniques for filter construction. A SAR ADC includes an SAR for receiving an analog input signal and outputting a digital decision, a digital-to-analog converter and logic circuitry for converting the digital decision of the SAR to a present analog residue for a present conversion cycle, a filter for processing a previous analog residue from a previous conversion cycle, and for feeding a processed previous analog residue back to the SAR, a summer for summing the processed previous analog residue from the filter and the present analog residue, and generating a summer output, and a comparator for comparing the summer output and a first reference signal and generating a comparator output. The filter includes a capacitor array for filtering the previous analog residue to generate the processed previous analog residue.

Abstract: A voltage regulator circuit having an internally compensated effective series resistance includes a control circuit to generate an out current at a regulated output voltage based on a reference voltage. The control circuit includes an amplifier, a resistive element to feedback output voltage to an input of the amplifier, and a compensation circuit to couple the internally compensated effective series resistance into the control circuit. The compensation circuit includes a first current sense device to generate a first sensed current proportional to a current through an N-type pass device, a second current sense device arranged to generate a second sensed current proportional to the current through the N-type pass device, and a bias circuit coupled to sink the first sensed current and the second sensed current to reduce a bias voltage across the resistive element below a threshold voltage.

Abstract: Various embodiments of a compact sensor module are disclosed herein. The sensor module can include a stiffener and a sensor substrate wrapped around a side of the stiffener. A sensor die may mounted on the sensor substrate. A processor substrate may be coupled to the sensor substrate. A processor die may be mounted on the processor substrate and may be in electrical communication with the sensor die.

Abstract: An analog front end (AFE) system for substantially eliminating quantization error or noise can combine an input of an integrator circuit in the AFE system with an input of the digital-to-analog converter (DAC) circuit in the feedback loop of the AFE system. By combining the input of the integrator with the input of the DAC circuit in the feedback loop, the in-band quantization noise of the filter can be substantially eliminated, thereby improving measurement accuracy.

Abstract: To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.

Abstract: Device for optically detecting smoke and implementing thereof. Apparatus and methods for detecting the presence of smoke in a small, long-lasting smoke detector are disclosed. Specifically, the present disclosure shows how to build a very compact housing around the smoke detector while keeping the reflections from the housing structure to a very low value while satisfying all the other peripheral needs of fast response to smoke and preventing ambient light. This allows very small measurements of light scattering of the smoke particles to be reliable in a device resistant to the negative effects of dust. In particular, geometrical optical elements, e.g., cap and optical defection elements, are disclosed.

Abstract: Device for optically detecting smoke and implementing thereof. Apparatus and methods for detecting the presence of smoke in a small, long-lasting smoke detector are disclosed. Specifically, the present disclosure shows how to build a very compact housing around the smoke detector while keeping the reflections from the housing structure to a very low value while satisfying all the other peripheral needs of fast response to smoke and preventing ambient light. This allows very small measurements of light scattering of the smoke particles to be reliable in a device resistant to the negative effects of dust.