Abstract: An example embodiment of an active cascode circuit has a control circuit for control of the gate to source voltage (VGS) of at least one transistor in the active cascode circuit. The embodiment may be configured so that control of the VGS also controls the voltage Vin on the input. Vin may be adjusted without altering the device geometry or changing the drain current. This allows for better control and optimization of available headroom for the input voltage in low voltage designs and also results in higher active cascode circuit bandwidth and/or higher output impedance (Rout) for a given power level.

Abstract: A plethysmography (“PPG”) measurement system may include at least one source of PPG radiation and at least one auxiliary sensor for detection of PPG radiation. The radiation source emits a portion of the PPG radiation toward a subject and another portion along an optical path for direct communication between the PPG radiation source and the auxiliary sensor. The auxiliary sensor may develop a profile against which measurements from primary PPG sensors, which receive light returning from the subject, may be compared. From this comparison, new PPG signals may be generated that exhibit lower noise than the PPG signals output by PPG sensors. These noise mitigation techniques may be used advantageously by a PPG system to generate more accurate measurements and also to reduce power consumption by the radiation sources.

Abstract: Apparatus and methods for electronic amplification are provided. In one embodiment, an amplifier includes first and second input terminals, an amplification circuit, a feedback circuit, and a current mirror. The amplification circuit includes a non-inverting voltage input electrically connected to the first input terminal and to a bias voltage, an inverting voltage input electrically connected to the second input terminal, a voltage output, and a current output. The amplifier includes a first feedback path from the voltage output to the inverting voltage input through the feedback circuit and a second feedback path from the current output to the inverting voltage input through the current mirror, which can mirror a current from the current output to generate a mirrored current. A current source such as a transducer can provide an input current between the first and second input terminals, and the mirrored current can substantially match the input current.

Abstract: Apparatus and methods to increase the range of a signal processing circuit. A system uses floating bias circuits coupled to a signal processing circuit to increase the range of power supplies that can be used with the signal processing circuit, while maintaining the components of the signal processing circuit within a breakdown voltage threshold. As the voltage level of the data signal varies, the voltage level of the floating bias circuits varies as well.

Abstract: In an example embodiment, a circuit is provided that includes a pre-fetch unit configured to pre-fetch instructions and data from a flash used by a microprocessor and decode the instructions and data without storing and accessing an address history, wherein the pre-fetcher is aware of the microprocessor's instruction set and performs parallel direct decode of each instruction accessed from the flash. In an example embodiment, method for pre-fetching instructions from a flash to a microprocessor is provided that includes reading a line of program code from the flash, assigning the instructions or data in the line to a thread in a hopper maintained in a cache, decoding the instructions to detect branches, and initiating a fetch from the flash if the target instruction is not found in one of the hoppers in the cache, building and maintaining predicted threads of instructions most likely to be executed by the microprocessor.

Abstract: Apparatus and methods for reducing input bias current of electronic circuits are provided herein. In certain implementations, an electronic circuit includes a first input terminal, a second input terminal, an input circuit, and a plurality of input switches including at least a first input switch and a second input switch. The first input switch is electrically connected between the first input terminal and a first input of the input circuit, the second input switch is electrically connected between the second input terminal and a second input of the input circuit, and the first and second input switches can be opened and closed using a clock signal. The electronic circuit further includes a charge compensation circuit for compensating for charge injection through the first and second input switches during transitions of the clock signal.

Abstract: An electrical circuit includes a photodiode that receives a light signal from a light source and generates a photocurrent signal, a trans-impedance amplifier that amplifies the photocurrent signal and generates a low noise signal, and a high pass filter that converts the low noise signal into an alternating current (AC) signal having a positive amplitude, a negative amplitude, and a zero cross-over point between the positive amplitude and the negative amplitude. The electrical circuit also includes a positive integrating amplifier that receives the positive amplitude of the AC signal and generates a positive integrated value over an integration period, and a negative integrating amplifier that receives the negative amplitude of the AC signal and generates a negative integrated value over the integration period. The electrical circuit further includes at least one analog-to-digital converter that receives the positive and negative integrated values.

Abstract: Apparatus and methods are disclosed related to low-voltage radio transmitters with high spectral purity. One such apparatus includes a baseband path with a predistortion stage, a programmable filter, and an upconverter core. In an embodiment, the programmable filter is placed between the predistortion stage and the upconverter core. In an embodiment, the programmable filter is configured by a controller to reject out-of-band noise introduced at the predistortion stage or earlier.

Abstract: Signal IO protection devices referenced to a single supply are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power supply network, such as a power low supply network or a power high supply network. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. In other implementations, a protection device includes first and second SCRs for providing protection between the signal node and the power low supply network or between the signal node and the power high supply network, and the SCR structures are integrated in a common circuit layout. The protection devices are suitable for single cell data conversion interface protection to a single supply in sub 3V operation.

Abstract: Apparatus and methods reduce common-mode error. An integrated circuit includes a plurality of signal channels, a first proxy channel, and a subtraction block. The signal channels are configured to receive a plurality of input signals and to generate a plurality of output signals, and each of the signal channels has a substantially similar circuit topology. The first proxy channel has a substantially similar circuit topology as the plurality of signal channels, and includes an output that can vary in relation to a common-mode error of the signal channels. The subtraction block is configured to generate a plurality of modified output signals by using the output of the first proxy channel to reduce the common-mode error of the plurality of output signal channels.

Abstract: Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.

Abstract: In one example implementation, the present disclosure provides a direct current (DC) restoration circuit for restoring the DC component of a synchronization signal provided over an alternating current (AC) coupled link from a transmitting circuit to a receiving circuit. During a period of inactivity in the synchronization signal, the synchronization signal may experience a drift towards the common mode, and may affect the ability for the synchronization signal to properly trigger the receiving circuit. The DC restoration circuit is configured to hold the synchronization signal steady during the period of inactivity, and allow the AC component of the synchronization signal pass through to the receiving circuit during the period of activity to alleviate the problem of baseline drift in the synchronization signal.

Abstract: The present disclosure provides embodiments of an improved current steering switching element for use in a digital to analog (DAC) converter. Typically, each current steering switching element in the DAC converter provides a varying set of currents for converting a digital input signal. Generally, the switches and drivers in the current steering switching elements are scaled down proportionally to the current being provided by the current steering switching element according to a ratio as less and less current is being driven by the switching element in order to overcome timing errors. However, device sizes are limited by the production process. When a switch is not scaled proportionally to the current, settling timing errors are present and affects the performance of the DAC. The improved current steering switching element alleviates this issue of timing errors by replacing the single switch with two complementary current steering switches.

Abstract: Various embodiments of a compact sensor module are disclosed herein. The sensor module can include a stiffener and a sensor substrate having a mounting segment and a first wing segment extending from the mounting segment. The first wing segment may be folded around an edge of the stiffener. A sensor die may be mounted on the mounting segment of the sensor substrate. A processor substrate may be coupled to the sensor substrate. A processor die may be mounted on the processor substrate and may be in electrical communication with the sensor die.

Abstract: Apparatus and methods are disclosed related to managing characteristics of a mobile device based upon capacitive detection of materials proximate the mobile device, a capacitive gesture system that can allow the same gestures be used in arbitrary locations within range of a mobile device. One such method includes receiving a first capacitive sensor measurement with a first capacitive sensor of the mobile device. The method further includes determining a value indicative of a material adjacent to the mobile device based on a correspondence between the first capacitive sensor measurement and stored values corresponding to different materials. The method further includes sending instructions to adjust a characteristic of the mobile device based on the determined value indicative of the material adjacent to the mobile device. In certain examples, gesture sensing can be performed using capacitive measurements from the capacitive sensors.

Abstract: Apparatus and methods for analog-to-digital conversion of quadrature receive signals are provided herein. In certain implementations, a transceiver system includes at least a first pair of analog-to-digital converters (ADCs) associated with a first quadrature receiver channel and a second pair of ADCs associated with a second quadrature receiver channel. The first and second pairs of ADCs can provide analog-to-digital conversion of the same receive signal, but can have different noise profiles relative to one another, such as a low pass noise profile and a band pass noise profile. The transceiver system can further include a reconstruction filter for combining the outputs of at least the first and second pairs of ADCs to generate output signals associated with a lower overall noise profile relative to that of either pair of ADCs alone.

Abstract: Aspects of this disclosure relate to reference switchover. In one embodiment, an apparatus includes a phase error detector, a phase alignment detector, and a selection circuit. The phase error detector is configured to generate an indication of a relative phase difference between a first reference clock signal and a second reference clock signal. The phase alignment detector is configured to receive the indication of the relative phase difference and determine when the relative phase difference satisfies a preset threshold. The selection circuit is configured to transition from providing the first reference clock signal as a clock system reference signal to providing the second reference clock signal as the clock system reference signal responsive to the phase alignment detector detecting that the relative phase difference satisfies the preset threshold.

Abstract: A method for forming an alignment feature for back side wafer processing in a wafer fabrication process involves forming a trench into but not entirely through a wafer from a top side of the wafer; forming a contrasting material on surfaces of the trench; and grinding a bottom side of the wafer to expose the trench using the handling wafer to handle the wafer during such grinding, wherein the contrasting material lining the exposed trench provides an alignment reference for precise alignment of the wafer for back side processing the wafer.

Abstract: In one example embodiment, a programmable capacitor array is provided for low distortion and minimizing linearity degradation of an input (Vin) by utilizing control circuitry to switch on and off an array of MOSFET switches. The control circuitry turns on a MOSFET to load a capacitance on Vin and turns off the MOSFET to remove the capacitance from Vin in response to a Din control signal. When the intention is to load Vin with the capacitance, the MOSFET is left on continuously. When the intention is to remove or unload the capacitance from Vin, the MOSFET is primarily turned off, however, the MOSFET is still periodically turned on with appropriate voltage levels in response to a clock signal for periods of time when the loading of the capacitance on Vin is tolerable to the system, thereby ensuring minimal linearity degradation of Vin due to the programmable capacitor array system.

Abstract: A system for correcting distortion effects in a distorted image includes a memory controller for reading pixels (corresponding to a subset region in a destination image) of the distorted image from a system memory to local memory. A look-up table stores an offset and interpolation weight for each pixel, and an ALU computes, using stored values only in the local memory, values of each of the pixels in the region in the destination image.