Abstract: A memory mechanism for providing semaphore functionality in a multi-master processing environment is disclosed. An exemplary memory unit includes a memory controller that manages access to a shared memory. The memory controller includes a semaphore context monitor associated with each master having access to the shared memory. A semaphore context monitor associated with a semaphore-capable master is activated by the semaphore-capable master (for example, by exclusive request signal(s) received by memory controller from semaphore-capable master). A semaphore context monitor associated with a non-semaphore-capable master is activated by the memory controller (for example, by exclusive request signal(s) generated by the memory controller).

Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.

Abstract: An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter.

Abstract: Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.

Abstract: Circuits for generating a PTAT voltage as a base-emitter voltage difference between a pair of bipolar transistors. The circuits may form unit cells in a cascading voltage reference circuit that increases the PTAT voltage with each subsequent stage. The bipolar transistors are controlled using a biasing arrangement that includes an MOS transistor connected to a current mirror that provides the base current for the bipolar transistors. A voltage reference is formed by combining a PTAT voltage and a CTAT voltage at the last stage. The voltage reference may be obtained from the voltage at an emitter of one of the bipolar transistors in the last stage.

Abstract: A device and method for measuring active and reactive powers of an alternating current includes receiving a first signal representing a current and a second signal representing a voltage, in which the current includes a phase offset with respect to the voltage, calculating an active power and reactive power based on the first and second signals, and calibrating the calculated active and reactive powers with respect to the phase offset using first and second constants, in which the first and second constants respectively correspond to a sine value and a cosine value of the phase offset.

Abstract: A voltage generator may include a plurality of charge pumps, plural sets of delay pipelines and a phase controller. Given M delay pipelines having N stages each, there may be M*N charge pumps each having a triggering input coupled to a respective stage or a respective pipeline. The phase controller may include a plurality of phase control stages interconnecting among the delay pipelines to induce timing offsets among the outputs of the delay stage. In an alternate design, intermediate nodes among the pipeline's delay stages may be coupled to triggering inputs of a sub-set of the charge pumps. The phase controller may have a plurality of phase control stages coupled, respectively, between the intermediate nodes of the delay pipeline and intermediate nodes of the phase control stages may be coupled to triggering inputs of another sub-set of the charge pumps.

Abstract: A mobile TV system architecture for a mobile terminal that reduces the processing required by the main processor during reception of digital broadcasts such as DVB-H. The mobile terminal architecture includes a main processor system and a mobile TV receiver device. The mobile TV receiver device includes units for SI/PSI processing, IP processing and decryption engine. The SI/PSI (service information/program specific information) processing unit receives non-protected transport stream (TS) packets and extracts SI/PSI tables which can be stored in memory local to the receiver device. The IP processing unit receives decrypted error-corrected protected packets containing multimedia content. The receiver device may include an HTTP server for communicating with a browser application running on the main processor system. The browser application presents multimedia content, received via HTTP, corresponding to a URL entered or selected by a user.

Abstract: In an example, a differential amplifier is disclosed that is configured to realize low noise with decreased overall system current. The differential amplifier may include a first amplifier stage and a second amplifier stage arranged in series, wherein a pull-up current iH flowing as a single bias current iB=iH flows into the first stage. A single pull-down current iT sources to ground from the second stage, wherein iH=iT=iB substantially. In certain embodiments, the transconductance of the second stage may be increased by providing two transconductors coupled at their base nodes.

Abstract: In comb drive vibratory gyroscopes, drive-induced Coriolis accelerometer offset is effectively canceled by demodulating the output during equal times of in-phase and anti-phase drive of the shuttle with respect to the velocity signal used for angular rate demodulation. This reduces or eliminates the corresponding thermal and die-stress effects otherwise needing calibration.

Abstract: Mechanical resonators including doped piezoelectric active layers are described. The piezoelectric active layer(s) of the mechanical resonator may be doped with a dopant type and concentration suitable to increase the electromechanical coupling coefficient of the active layer. The increase in electromechanical coupling coefficient may all for improved performance and smaller size mechanical resonators than feasible without using the doping.

Abstract: One aspect of this disclosure is an apparatus including an oscillator that includes a secondary LC circuit to increase a tuning range of the oscillator and/or to reduce a phase noise of the oscillator. Another aspect of this disclosure is an apparatus that includes oscillator with a primary LC circuit and a secondary LC circuit. This oscillator can operate in a primary oscillation mode or a secondary oscillation mode, depending on whether oscillation is set by the primary LC circuit or the secondary LC circuit.

Abstract: A bidirectional current sensor circuit can be configured to generate a scaled version of a load current using a first transistor from a power regulator output stage and a second transistor that can be a mirror or scaled version of the first transistor. A trim circuit can be provided to correct gain errors under current sinking or current sourcing conditions. In an example, the bidirectional current sensor circuit can be configured to detect a polarity or a magnitude of a current signal that is used to operate a thermoelectric device.

Abstract: In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from faults in the interconnect itself or in any of the connected peripherals. To provide sufficient fault tolerance, a safety node is inserted between an upstream master section and a downstream slave section of an on-chip bus hierarchy or network. The safety node provides a programmable timeout monitor for detecting a timeout condition for a transaction. If timeout has occurred, the safety node transmits a dummy response back to the master, assumes the role of a master, and waits for the slave device to respond. Furthermore, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting a dummy response to those subsequent requests, thus enabling these masters to avoid deadlock or stall.

Abstract: Various embodiments of an integrated device package are disclosed herein. The package may include a leadframe having a first side and a second side opposite the first side. The leadframe can include a plurality of leads surrounding a die mounting region. A first package lid may be mounted on the first side of the leadframe to form a first cavity, and a first integrated device die may be mounted on the first side of the leadframe within the first cavity. A second integrated device die can be mounted on the second side of the leadframe. At least one lead of the plurality of leads can provide electrical communication between the first integrated device die and the second integrated device die.

Abstract: A substrate for an inertial sensor system includes a plurality of electrode arrangements, each electrode arrangement including an acceleration sensor electrode and a pair of quadrature adjusting electrodes on opposite sides of the acceleration sensor electrode, where each electrode arrangement is capable of being overlaid by a corresponding plate of a shuttle such that the plate completely overlays the acceleration sensor electrode and partially overlays the pair of quadrature adjusting electrodes on opposite sides of the acceleration sensor electrode such that capacitive coupling between the plate and each of the quadrature adjusting electrodes is dependent upon the rotational position of the at least one shuttle while capacitive coupling between the plate and the acceleration sensor electrodes is substantially independent of the rotational position of the at least one shuttle.

Abstract: Apparatus and methods for multiphase oscillators are provided. In certain implementations, an oscillator system includes a first multiphase oscillator and a second multiphase oscillator that are phase and frequency-locked. Additionally, the first and second multiphase oscillators are phase-locked by an amount of phase shift that provides colocated clock signal phases of relatively wide angular distances, which can be used by the oscillators' amplification circuits. The first and/or second multiphase oscillators include one or more amplification circuits that operate using at least one clock signal phase generated by the first multiphase oscillator and using at least one clock signal phase generated by the second multiphase oscillator.

Abstract: An accurate, cost-efficient temperature sensor may be integrated into an integrated circuit (IC) using common materials as the IC's interconnect metallization. The temperature sensor may include an impedance element having a length of metal made of the interconnect metal, a current source connected between a first set of contacts at opposite ends of the impedance element, and an analog-to-digital converter connected between a second set of contacts at opposite ends of the impedance element. The temperature sensor may exploits the proportional relationship between the metal's resistance and temperature to measure ambient temperature. Alternatively, such a temperature sensor may be used on disposable chemical sensors where the impedance element is made of a common metal as conductors that connect a sensor reactant to sensor contacts. In either case, because the impedance element is formed of a common metal as other interconnect, it is expected to incur low manufacturing costs.

Abstract: The present disclosure provides a memory interconnection architecture for a processor, such as a vector processor, that performs parallel operations. An example processor may include a compute array that includes processing elements; a memory that includes memory banks; and a memory interconnect network architecture that interconnects the compute array to the memory. In an example, the memory interconnect network architecture includes a switch-based interconnect network and a non-switch based interconnect network. The processor is configured to synchronously load a first data operand to each of the processing elements via the switch-based interconnect network and a second data operand to each of the processing elements via the non-switch-based interconnect network.

Abstract: The circuit of the present disclosure is a high-speed precision clamp (voltage limiter) for overvoltage or undervoltage protection. One aspect of the circuit includes using a peak detector in the feedback path of a clamp having a super-diode architecture. The resulting circuit performs well for high-speed applications. The peak detector can be replicated (at least in part) to accommodate a multiplicity of phase-shifted input voltages by using only one common peak detection capacitor and ensuring area savings in integrated-circuit implementations.