Abstract: Remote evaluation, e.g., web-based evaluation, lowers the evaluation barrier by allowing an engineer to gain experience with an integrated circuit (IC) using a client (e.g. a web browser) on a remote computer (e.g., a machine remote from the IC being evaluated but local to the engineer) to activate a test set-up that is maintained at a location that is far away from the engineer.

Abstract: Provided herein are high frequency signal attenuators. In certain configurations, an integrated circuit includes a signal conductor that carries a radio frequency (RF) signal, a shield conductor routed with the signal conductor and biased with a ground voltage, and an attenuation circuit that provides a controllable amount of attenuation to the RF signal. The attenuation circuit includes a shunt circuit electrically connected between a signal tapping position of the signal conductor and a shield tapping position of the shield conductor. Connecting the shunt circuit in this manner enhances high frequency performance by reducing a length of an effective loop from the signal conductor to an adjacent portion of the shield conductor.

Abstract: An optical sensor module is disclosed. The optical sensor module can include a housing comprising an air cavity. An optical emitter die can be disposed in the air cavity of the housing. A top surface of the optical emitter die can face a first side of the housing, the optical emitter die configured to emit light towards the first side of the housing. An optical sensor die can be disposed in the air cavity of the housing adjacent the optical emitter die. The optical sensor die can be spaced from the optical emitter die by a lateral distance. A top surface of the optical sensor die can face the first side of the housing. There may be no septum between the optical sensor die and the optical emitter die that optically separates the optical sensor die and the optical emitter die.

Abstract: A dynamically tunable transconductor includes a voltage-to-current converter stage for generating a current signal based on a voltage signal; and a current scaling stage for scaling the current signal by a scaling factor to achieve a particular transconductance. Current scaling stage includes a coarse tune mechanism having an associated coarse tune step and a fine tune mechanism having an associated fine tune step, where the scaling factor is a ratio of the coarse tune step to the fine tune step. A delta-sigma modulator can implement the transconductor to generate loop filter coefficients by dynamically tuning the transconductance to achieve a particular resistance.

Abstract: The present application relates generally to programmable impedances and employs an auxiliary impedance in parallel to a primary programmable impedance to augment the performance of the primary programmable impedance at lower impedance values.

Abstract: In an isolation system, different analog to digital converters (“ADCs”) are provided on a first side of an isolation barrier. Outputs from the ADCs may be merged into a common data stream and communicated across the isolation barrier by a single isolation device. The ADCs may sample independent signals or may sample a common signal. When the ADCs sample a common signal, the system may monitor the input signal for fault conditions. During no fault operation, results of an analog-to-digital conversion may be communicated across an isolation barrier by an isolation device. During a fault condition, data representing the fault condition may replace the ADC data in communication across the isolation barrier. Fault conditions may be signaled by unique data patterns that can be distinguished from ADC data.

Abstract: A MEMS switch has a base formed from a substrate with a top surface and an insulator layer formed on at least a portion of the top surface. Bonding material secures a cap to the base to form an interior chamber. The cap effectively forms an exterior region of the base that is exterior to the interior chamber. The MEMS switch also has a movable member (in the interior chamber) having a member contact portion, an internal contact (also in the interior chamber), and an exterior contact at the exterior region of the base. The contact portion of the movable member is configured to alternatively contact the interior contact. A conductor at least partially within the insulator layer electrically connects the interior contact and the exterior contact. The conductor is spaced from and electrically isolated from the bonding material securing the cap to the base.

Abstract: Existing synchronization methods can be inefficient in hardware-assisted implementations because of the effects of various jittery events. Thus, a method and an apparatus are provided to synchronize a slave device's clock to a master device's clock for a hardware-assisted implementation. The method can include the receipt of three messages. Time differences are determined based on a time extracted from two of the messages and a time of receipt of a different one of the messages. The slave device's clock can be adjusted based on these time differences. Thus, this method, which can include a dynamic weighted average to compute and implement the synchronization, can synchronize the clock of the slave device to the clock of the master device in a faster time interval.

Abstract: An apparatus comprises a switching circuit, an error amplifier circuit, a current threshold circuit, and an over-current detection circuit. The switching circuit provides a switching duty cycle that includes a charge portion and a discharge portion. The error amplifier circuit generates an error signal representative of a difference between a target voltage value and a voltage at an output of the voltage regulator circuit. The switching circuit adjusts the switching duty cycle to regulate the voltage at the output using the error signal and a reference waveform signal. The current threshold circuit generates an adaptive peak current limit threshold. The over-current detection circuit generates an over-current signal when the reference waveform signal satisfies the adaptive peak current limit threshold during the charging portion of the switching cycle. The switching circuit interrupts one or more switching cycles when the reference waveform signal satisfies the adaptive peak current limit threshold.

Abstract: The present application relates generally to programmable impedances and employs an auxiliary impedance in parallel to a primary programmable impedance to augment the performance of the primary programmable impedance at lower impedance values.

Abstract: Adaptive biasing circuits for input differential pairs of a buffer or an amplifier adapt to autozero currents for discrete pair selection or continuous pair selection. The adaptive biasing circuits include a multistage device including current source and follower devices with a plurality of switches for a two-phase operation: autozero and amplifying phases. During an autozero phase, input differential pairs are isolated from subsequent stages and biasing currents are determined for autozeroing of input offset voltages. During an amplifying phase, both input differential pairs can be coupled to subsequent stages for continuous selection or a selected input differential pair can be coupled to subsequent stages for discrete selection.

Abstract: A system and method for removing noise from images are disclosed herein. An exemplary system includes an edge-detection-based adaptive filter that identifies edge pixels and non-edge pixels in an image and selects a filtering technique for at least one non-edge pixel based on a comparison of the at least one non-edge pixel to a neighboring pixel region, wherein such comparison indicates whether the at least one non-edge pixel is a result of low-light noise.

Abstract: The present disclosure provides a processor, and associated method, for performing parallel processing within a register. An exemplary processor may include a processing element having a compute unit and a register file. The register file includes a register that is divisible into lanes for parallel processing. The processor may further include a mask register and a predicate register. The mask register and the predicate register respective include a number of mask bits and predicate bits equal to a maximum number of divisible lanes of the register. A state of the mask bits and predicate bits is set to respectively achieve enabling/disabling of the lanes from executing an instruction and conditional performance of an operation defined by the instruction. Further, the processor is operable to perform a reduction operation across the lanes of the processing element and/or generate an address for each of the lanes of the processing element.

Abstract: Switching interference is a primary artifact which affects the accuracy of arc detectors. To address switching interference, conventional arc detectors employ computationally intensive techniques which are often designed specifically for a target application. Thus, conventional arc detectors require a significant amount of hardware to accurately detect arc faults, which can increase costs of the power systems and prohibit wide deployment of arc detectors. With improved signal processing, a unique method for arc detection can accurately detect arc faults efficiently while tolerate switching interference from an inverter of the power system. Specifically, the method provides accurate but efficient arc detection by using a small Fast Fourier Transform with coherent sampling that is accomplished with a common clock generator in combination with signal conditioning. The overall system implementing the method is also programmable to suit a variety of target applications.

Abstract: Apparatus and method for clock and data recovery are disclosed. A reset circuit counts clock cycles between edges of an input signal and resets a signal processing circuit that performs acquisition and tracking of a data stream when the clock cycle count is outside of a range. The signal processing circuit is further configured to perform acquisition and tracking according to a corrected data rate, which can be generated by data rate adjustment through a phase error correcting control loop and/or dithering between two data rates.

Abstract: A multichannel system, including a multiplexer having inputs for a plurality of input channels, and a pre-charge buffer having a plurality of inputs coupled to an input of the multiplexer, and an output coupled to a multiplexer output. The multichannel system may stand alone, or may be coupled to a receiving circuit having an input coupled to an output of the multiplexer. In some instances, the receiving circuit is an analog to digital converter.

Abstract: Apparatus and methods for reducing glitches in digital step attenuators are disclosed. By configuring a multi-bit DSA such that an attenuation control block changes a plurality of control signals in a manner sequencing individual switches of the DSA, glitches can be reduced and RF signal behavior can be enhanced. The sequence, based upon a unit time delay, causes the transient attenuation value to be bounded between a minimum and maximum and can improve settling time.

Abstract: Many conventional video processing algorithms attempting to detect human presence in a video stream often generate false positives on non-human movements such as plants moving in the wind, rotating fan, etc. To reduce false positives, a technique exploiting temporal correlation of non-human movements can accurately detect human occupancy while reject non-human movements. Specifically, the technique involves performing temporal analysis on a time-series signal generated based on an accumulation of foreground maps and an accumulation of motion map and analyzing the running mean and the running variance of the time-series signal. By determining whether the time-series signal is correlated in time, the technique is able to distinguish human movements and non-human movements. Besides having superior accuracy, the technique lends itself to an efficient algorithm which can be implemented on low cost, low power digital signal processor or other suitable hardware.

Abstract: Apparatus and methods for controlling overshoot in digital step attenuators are disclosed. By configuring a multi-bit DSA such that an attenuation control block changes a plurality of control signals in a manner preventing a series cascade of attenuation units from having a transient attenuation value less than an initial and final value of attenuation, an overshoot condition can be prevented. Control signals transition the attenuation units to a first state of attenuation before they transition attenuation units to a second state of insertion.

Abstract: A microphone circuit assembly for an external application processor, such as a programmable Digital Signal Processor, may include a microphone preamplifier and analog-to-digital converter to generate microphone signal samples at a first predetermined sample rate. A speech feature extractor is configured for receipt and processing of predetermined blocks of the microphone signal samples to extract speech feature vectors representing speech features of the microphone signal samples. The microphone circuit assembly may include a speech vocabulary comprising a target word or target phrase of human speech encoded as a set of target feature vectors and a decision circuit is configured to compare the speech feature vectors generated by the speech feature extractor with the target feature vectors to detect the target speech word or phrase.