Abstract: An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a semiconductor substrate having formed therein a bidirectional semiconductor rectifier (SCR) having a cathode/anode electrically connected to a first terminal and an anode/cathode electrically connected to a second terminal. The integrated circuit device additionally includes a plurality of metallization levels formed above the semiconductor substrate. The integrated circuit device further includes a triggering device formed in the semiconductor substrate on a first side and adjacent to the bidirectional SCR.

Abstract: Transmitter noise cancellation may be applied on a channel by channel basis to active channels of an incoming radio frequency signal received at a receiver. A noise cancellation filter may be provided for each active channel in a predetermined signal band. Applying noise cancellation on a per active channel basis instead of to the entire receive band may substantially reduce the filtering requirement and number of filter coefficients or taps to save power and reduce manufacturing costs. Channelized transmitter noise cancellers, multi transmitter-receiver cross coupling cancellers, and hybrid full signal band and channelized transmitter noise cancellers are also provided.

Abstract: The present invention relates to electrical measurement apparatus (10). The electrical measurement apparatus (10) comprises a measurement arrangement (20,24) configured to be disposed in relation to an electrical circuit (12,14,16,18) which bears an electrical signal, the measurement arrangement (20,24) being operative when so disposed to measure the electrical signal. The electrical measurement apparatus (10) further comprises a signal source (22) operative to apply a reference input signal to the measurement arrangement (20,24) whereby an output signal from the measurement arrangement comprises an electrical output signal corresponding to the electrical signal and a reference output signal corresponding to the reference input signal, the reference input signal having a substantially piecewise constant form which is repeated over each of plural cycles.

Abstract: A bus driver is provided that can withstand over voltages being applied to its output terminal without the protection circuit detracting from the voltage swing that can be provided by the driver. The circuit arrangement also allows transistors having good on state resistance and large tolerance of drain-to-source voltages to be used.

Abstract: The present application relates in one aspect to a method of controlling diaphragm excursion of an electrodynamic loudspeaker. The method comprises dividing the audio input signal into at least a low-frequency band signal and a high-frequency band signal by a band-splitting network and applying the low-frequency band signal to a diaphragm excursion estimator. The instantaneous diaphragm excursion is determined based on the low-frequency band signal. The determined instantaneous diaphragm excursion is compared with an excursion limit criterion. The low-frequency band signal is limited based on a result of the comparison between the instantaneous diaphragm excursion and the excursion limit criterion to produce a limited low-frequency band signal which is combined with the high-frequency band signal to produce an excursion limited audio signal.

Abstract: A bias current generators that may be implemented in low power environments is described. The current generator can be implemented without using resistors and may be used to generate reference currents and voltages. It may also be used to generate voltage references where the output of the circuit is to at least a first order temperature independent.

Abstract: An active voltage divider circuit is provided comprising: a first node; a second node; a third node; multiple FET load devices coupled in series between the first node and the second node; multiple first switches, each associated with a different FET load device and configured to selectably couple a respective associated bypass circuit between source and drain of its associated FET load device; and second switch circuitry configured to selectably couple a drain of a FET load device, from among the multiple FET load devices, to the third node.

Abstract: A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.

Abstract: An inverter based on a compound semiconductor uses a depletion mode transistor as the pull-up device, and a current source to bias the pull-up device. The current source is electrically coupled to a source terminal of the pull-up device. As a result, the current source continues to conduct current through the pull-up device, whether the inverter output is high or low, to ensure rapid response of the inverter.

Abstract: A successive approximation routine (SAR) analog-to-digital converter integrated circuit can include multiple analog-to-digital converters (ADCs) sharing a reference voltage that can be perturbed by a capacitor array of a digital-to-analog converter (DAC) sampling the reference voltage, which can limit conversion accuracy. Synchronizing every bit trial across the ADCs can improve accuracy but can slow the conversion. Synchronizing a subset of at least one, but fewer than N, bit trials across ADCs can help obtain both speed and robustness. This selected subset can include bit trials corresponding to pro-defined critical events, such as those events for which a stable reference voltage node is particularly desirable.

Abstract: Apparatus for detecting a presence of a target in a room is disclosed. The apparatus includes a motion-sensitive passive infrared (PIR) sensor, an imaging sensor, and a control unit. The PIR sensor is adapted to provide a motion signal, while the imaging sensor is adapted to generate at least a first image and a second image. The control unit is adapted to provide either a first signal or a second signal, depending on the strength of the motion and a comparison of the first and second images, where the first signal indicates a presence of the target and the second signal indicates an absence of the target. Also disclosed are a system for controlling lighting in a room, a method for detecting a presence of a target in a room, and a corresponding use of an apparatus for controlling lighting in a room.

Abstract: A sigma delta analog-to-digital converter (ADC) circuit comprises a capacitive gain amplifier circuit having a first input to receive an input voltage and a second input; a loop filter circuit connected to an output of the capacitive gain amplifier circuit; a sub-ADC circuit including an output and an input connected to an output of the loop filter circuit; and a digital-to-analog (DAC) circuit including a DAC input connected to the output of the sub-ADC circuit, and a DAC output connected to the second input of the capacitive gain amplifier.

Abstract: An apparatus comprises a delta-sigma analog-to-digital converter (ADC) and baseband processing circuitry. The delta-sigma ADC includes a plurality of integrator stages connected in series, including a first integrator stage operatively coupled to an input of the delta-sigma ADC; a main quantizer circuit including a main ADC circuit and a main digital-to-analog converter (DAC) circuit, wherein an input to the main ADC circuit is operatively coupled to the plurality of integrator stages; and a first feedback circuit path operatively coupled from an output of the first integrator stage to the input of the delta-sigma ADC, wherein the first feedback circuit path is configured to subtract an output voltage of the first integrator stage from the input of the delta-sigma ADC. The baseband circuitry is configured to activate the first feedback circuit path when detecting that the input voltage increases to cause distortion in the delta-sigma ADC.

Abstract: Apparatus and techniques described herein can include using an electronic circuit comprising a rectifier circuit, an open-circuit voltage (OCV) sampling circuit coupled to the output of the rectifier circuit, and a regulator circuit coupled to the output of the rectifier circuit. In an example, an isolation switch can be located between the regulator circuit and the rectifier circuit, the isolation switch configured to isolate the regulator circuit from the rectifier circuit for sampling of the open-circuit voltage by the open-circuit voltage sampling circuit. In another example, a buffer circuit can be used, such as placed in-line with a divider circuit between a divider circuit and an open-circuit voltage sampling capacitor. In this manner, the buffer circuit can provide a low output impedance, isolating the voltage sampling capacitor from the divider circuit.

Abstract: Continuous-time analog-to-digital converters (ADCs) such as continuous-time delta-sigma ADCs and continuous-time pipeline ADCs, has input resistor structure at the input. The input resistor structure is typically tunable, and the tunability is usually provided by metal-oxide semiconductor field effect transistor (MOSFET) switches. Core MOSFETs, which has a terminal-to-terminal voltage <1.0V, is used for the switches for performance reasons. However, a typical implementation can have reliability issues with overloading inputs. An improved input resistor protection circuit can solve this issue by generating on and off voltages for the switches inside the tunable resistor structure based on a summing node voltage where one side of the switch is connected.

Abstract: Mixers with improved linearity are disclosed. A diode or FET ring mixer is implemented with at least one parallel shunt element coupled with the ring mixer, the shunt element providing shunt to a diode or FET, for example, to reduce the effect of nonlinear or off resistance and/or capacitance. Linearity, isolation, symmetry, even order harmonics of the ring mixer, or any combination thereof can be improved as a result. The linearity of the ring mixer with parallel shunt resistors can be further improved by adding series resistors in the ring according to certain embodiments.

Abstract: Apparatus and methods for current sensing in switching regulators include a current sensing circuit to sense current of a power stage of a power converter. The power converter can include first and second transistors. The current sensing circuit comprises a transistor that is a scaled version of one of the transistors of the power converter. A circuit of the current sensing circuit matches a drain-to-source voltage of the transistor of the current sensing circuit to the corresponding transistor of the power converter. A current mirror generates a current that mirrors the current flowing through the transistor of the current sensing circuit. A first resistor converts the mirrored current to a current sensed signal.

Abstract: Methods and apparatus to reduce localized transistor operating temperature increases in fully integrated voltage regulator circuits are provided. Transistor self-heating effects are reduced by dispersing heat more evenly over the integrated circuit die, via use of nested voltage regulator circuits and/or use of more than one transistor in a voltage regulator circuit pass device. An electrically parallel-connected group of multiple individual integrated transistors may be laid out across cooler areas of the integrated circuit die, such as in substantially linear sets or rings of devices near the outer die perimeter. Each transistor in the group may better disperse its own heat if it is thermally segregated from other self-heating devices, as through a minimum physical layout spacing. Transistor bias voltage mismatch tolerances, load currents, and routing resistances may interrelatedly determine the number of individual transistors needed in a group.

Abstract: Wireless sensor nodes for enabling network connectivity in a wireless sensor network system are disclosed herein. An exemplary method includes receiving a Lightweight Machine-to-Machine (LWM2M) network packet from a network node over a network; using a media access control (MAC) layer to route the LWM2M network packet to a sensor node when a destination Internet Protocol (IP) address specified in the LWM2M network packet matches a virtual IP address; and using a network layer to route the LWM2M network packet to the sensor node when the destination IP address does not match a virtual IP address.

Abstract: A microprocessor circuit may include a software programmable microprocessor core and a data memory accessible via a data memory bus. The data memory may include sets of configuration data structured according to respective predetermined data structure specifications for configurable math hardware accelerators, and sets of input data for configurable math hardware accelerators, each configured to apply a predetermined signal processing function to the set of input data according to received configuration data. A configuration controller is coupled to the data memory via the data memory bus and to the configurable math hardware accelerators. The configuration controller may fetch the configuration data for each math hardware accelerator from the data memory and translate the configuration data.