Abstract: A stress shield for a plastic integrated circuit package is disclosed. A shield plate is attached by an adhesive to a top surface of an integrated circuit die such that the shield plate covers less than all of the top surface and leaves bond pads exposed. A molding material is applied over the shield plate and the integrated circuit die. The shield plate shields the integrated circuit die from stresses imparted by the molding material.

Abstract: Various embodiments efficiently detect the presence of an external capacitor electrically coupled to the output of a voltage regulator by perturbing the voltage output of the voltage regulator while the regulator is in operation and supplying, or ready to supply, regulated voltage to a load, and detecting the reaction of the regulator's output.

Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

Abstract: For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.

Abstract: An integrated constant time delay circuit utilized in continuous-time (CT) analog-to-digital converters (ADCs) can be implemented with an RC lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments. A Resistor-Capacitor “RC” lattice structure can be an alternative to a constant-resistance Inductor-Capacitor “LC” lattice implementation. ADC architectures benefit from the RC implementation, due to its ease of impedance scaling and smaller area.

Abstract: Provided herein are apparatus and methods for transconductance amplifiers, such as split cascode low-noise transconductance amplifiers (LNTAs). In an embodiment, an LNTA includes split current paths each coupled to a different mixer by way of a different alternating current (AC) coupling capacitor. The split current paths of the LNTA can be enabled during different modes of operation, such as when the input to the LNTA is within different frequency bands.

Abstract: A datapath circuit may include a digital multiply and accumulate circuit (MAC) and a digital hardware calculator for parallel computation. The digital hardware calculator and the MAC may be coupled to an input memory element for receipt of input operands. The MAC may include a digital multiplier structure with partial product generators coupled to an adder to multiply a first and second input operands and generate a multiplication result. The digital hardware calculator may include a first look-up table coupled between a calculator input and a calculator output register. The first look-up table may include table entry values mapped to corresponding math function results in accordance with a first predetermined mathematical function. The digital hardware calculator may be configured to calculate, based on the first look-up table, a computationally hard mathematical function such as a logarithm function, an exponential function, a division function and a square root function.

Abstract: A clock and data recovery (CDR) system may use one or more clock signals in sync with recovered data rate. By accumulating a dithering tuning counter value at a data oversampling rate, a plurality of single bit signals at multiples of the recovered data rate and in sync with the recovered data rate can be accurately generated while utilizing the full range of the accumulator. This plurality of clock signals can be used in various modules in the CDR system and other modules in a transceiver system incorporating the CDR system.

Abstract: Several features are disclosed that improve the operating performance of MEMS switches such that they exhibit improved in-service life and better control over switching on and off.

Abstract: Apparatus and methods for asynchronous clock mapping are provided herein. In certain configurations, an upstream server of a transport network generates clock difference data indicating a time difference between a server clock signal and a client clock signal, which have an asynchronous timing relationship with respect to one another. The clock difference data is generated with high precision by using one or more time-to-digital converters (TDCs). The clock difference data is included in a transmitted data stream, and is used by a downstream server to recover client information with enhanced accuracy.

Abstract: Improvements over existing data collection interfaces disclosed herein include, among other things, additional logic blocks (and associated timers, state machines, and registers) to off-load data collection and data processing prior to waking a microprocessor from a sleep mode. For example, an improved data collection interface collects a predetermined number of sensor values from a sensor while maintaining active a single communication session with the sensor over a pin of the interface. The microprocessor remains in the sleep mode for an entire duration of the single communication session. The data collection interface can reduce the likelihood of false starts of the microprocessor by using the logic blocks to verify that data meet preconditions prior to interrupting the microprocessor. The data collection interface can reduce the overall power consumption of a chip in which the microprocessor is integrated by a factor of at least about 2× (i.e., 50% reduction in power consumption).

Abstract: Aspects of this disclosure relate to a receiver for digital predistortion (DPD). The receiver includes an analog-to-digital converter (ADC) having a sampling rate that is lower than a signal bandwidth of an output of a circuit having an input that is predistorted by DPD. DPD can be updated based on feedback from the receiver. According to certain embodiments, the receiver can be a narrowband receiver configured to observe sub-bands of the signal bandwidth. In some other embodiments, the receiver can include a sub-Nyquist ADC.

Abstract: In high speed communication applications, e.g., optical communication, a variable gain amplifier is used for input signal amplitude normalization or for linear equalization. Traditionally a bipolar Gilbert multiplier circuit is used. When moving towards a low-power application, a modified circuit topology is implemented to reduce the minimum supply voltage requirement of the variable gain amplifier while ensuring that bias current levels remain substantially the same and achieving the same current switching capacity as the traditional circuit. As a result, the power consumption of the circuit can be greatly reduced. The modified circuit topology combines the amplifier and gain transistors and achieves gain programming using a voltage difference of two pairs of floating voltage sources.

Abstract: Remote evaluation, e.g., web-based evaluation, lowers the evaluation barrier by allowing an engineer to gain experience with an integrated circuit (IC) using a client (e.g. a web browser) on a remote computer (e.g., a machine remote from the IC being evaluated but local to the engineer) to activate a test set-up that is maintained at a location that is far away from the engineer.

Abstract: Microelectromechanical systems (MEMS) switches are described. The MEMS switches can be actively opened and closed. The switch can include a beam coupled to an anchor on a substrate by one or more hinges. The beam, the hinges and the anchor may be made of the same material in some configurations. The switch can include electrodes, disposed on a surface of the substrate, for electrically controlling the orientation of the beam. The hinges may be thinner than the beam, resulting in the hinges being more flexible than the beam. In some configurations, the hinges are located within an opening in the beam. The hinges may extend in the same direction of the axis of rotation of the beam and/or in a direction perpendicular to the axis of rotation of the beam.

Abstract: Mechanisms for generating dummy signals for use in reducing data dependent noise in DACs are disclosed. Disclosed mechanisms differentiate between odd and even bits of a digital data signal to be converted and generate dummy signals by inverting some of these bits and leaving other bits as they are (i.e. including them in their non-inverted form). One dummy signal is generated as a sequence of bits that is the same as a sequence of bits of a data signal except that every odd bit of the data signal is inverted. An alternative dummy signal is generated as a sequence of bits that is the same as a sequence of bits of a data signal except that every even bit is inverted. Generating dummy signals in this manner eliminates the need to use calibration, feedback, or transition detectors, advantageously resulting in increased timing margins and substantial power savings over existing implementations.

Abstract: For small cells, transceivers demand high performance while maintaining system efficiency. The present disclosure describes a highly integrated cellular transceiver that offers such features by providing one or more digital functions on-chip, onto the same die in the cellular transceiver. Effectively, the scope and boundary of the cellular transceiver is expanded to move beyond the data converters of the transceiver to include a variety of digital functions, thus integrating more of the signal chain in the cellular transceiver. Integration can greatly reduce complexity for the baseband processing, lower the cost of the overall transceiver system, reduce power consumption, and at the same time, benefit from improvements on the digital functions through integration.

Abstract: Provided herein are oscillator paths between an oscillator and mixers. In an embodiment, the oscillator paths include a first path between an oscillator and a first mixer and a second path between the oscillator and the second mixer, in which the first path is enabled in a first state (e.g., a low band state) and the second path is enabled in a second state (e.g., a high band state). The first path can include a radio frequency divider configured to receive a signal having the oscillator frequency and to divide the signal in frequency by a positive odd integer divisor greater than one, and a duty cycle correction circuit configured to receive an output from the radio frequency divider and provide an output having a duty cycle that is closer to 50% than the output from the divider. Such separate oscillator paths can, for example, enhance receiver performance.

Abstract: Apparatus and methods for biasing radio frequency (RF) switches are provided herein. In certain configurations, an RF switching circuit includes a field effect transistor (FET) switch electrically connected between a first terminal and a second terminal, and an adaptive biasing circuit that generates a bias voltage used in part to bias a gate of the FET switch. The adaptive biasing circuit includes a low pass filter that generates a low pass filtered voltage based on low pass filtering a voltage of the first terminal, a buffer circuit that receives the low pass filtered voltage and generates a buffered voltage, and a voltage shifting circuit that generates the bias voltage by shifting the buffered voltage by an amount of voltage that depends on a state of a switch control signal.

Abstract: A control apparatus is provided that can provide high dynamic resolution and is suitable for inclusion within an integrated circuit. The control apparatus receives a demand signal representing a desired value of a measurand, and a feedback signal representing a present value or a recently acquired value of the measurand. The processing circuit forms a further signal a further signal which is a function of the demand and feedback signals. The further signal is then subjected to at least an integrating function. The demand signal, feedback signal or the further signal is processed or acquired in a sampled manner. The use of such sampled, i.e. discontinuous, processing allows integration time constants to be synthesized which would otherwise require the use of unfeasibly large components within an integrated circuit, or the use of off-chop components. Both of these other options are expensive.