Abstract: An integrated circuit allows for the isolation of the input of an analog-to-digital converter (ADC) from a summing-node (SNS) algorithm. The integrated circuit contains a gating device that is controlled by bits of a flash analog-to-digital converter (ADC) to gate input samples to sub-ranges that are used by the SNS algorithm. A single sub-range is chosen to be used by the SNS algorithm.

Abstract: A circuit, system, machine-readable storage medium and method for detecting the presence of a leakage path in a multi-cell voltage source is described. The system includes a detection circuit, the detection circuit having a first, second and third amplifiers, a first input of the first amplifier connected to a first terminal of the voltage source and the first input of the second amplifier connected to a second terminal of the voltage source, a second input of each of the first and second amplifiers connected to a reference capacitor, and an output of each of the first, second and third amplifiers connected to a respective first, second and third outputs of the detection circuit; and a processor having inputs connected to the first and second outputs of the detection circuit.

Abstract: Embodiments of the present invention may provide a signal processor with a wide gain range. The signal processor may comprise at least a discrete step gain stage and a continuous variable gain amplifier (VGA) stage. The discrete step gain stage may comprise a programmable gain amplifier (PGA) (e.g., low noise amplifiers 1 and 2 (LNA1 and LNA2)). The VGA stage may provide a continuous range to compensate the LNAs gain steps. In one embodiment, the AGC controller enables an inherent hysteresis with the AGC step change if required.

Abstract: A system and method are provided for a PTAT cell with no resistors which can operate at low power, has less sensitivity to process variation, occupies less silicon area, and has low noise. Further, a system and method are provided to scale up the reference voltage and current through a cascade of unit cells. Still further, a system and method are provided for PTAT component to be fine-tuned, advantageously providing less process variability and less temperature sensitivity.

Abstract: A system and method to detect the fundamental frequency of an electric input signal using a feedback control loop including a phase error detector, a loop controller, and a digitally controlled oscillator. The frequency detector may detect the fundamental frequency of an electric input signal and produce an output signal representing the fundamental frequency of the electric input signal. The frequency detector may further include a filter that may be coupled to the frequency detector output signal in order to remove spurious tones or noise from the output signal.

Abstract: An analog-to-digital converter includes a plurality of sequentially cascaded stages, each stage including an amplifier and four copies of a circuit block including a flash and capacitors, in which the four copies of the circuit block operate interleavingly in a respective sample mode, pre-gain mode, gain mode, and reset mode of the circuit block, the copies of the circuit block in the sample mode, pre-gain mode, and reset mode are decoupled from the amplifier, and the copy of the circuit block in the gain mode is coupled to the amplifier to produce an output for a next following stage.

Abstract: In one embodiment, a measuring device may comprise two oscillators. The first oscillator may generate a local reference signal in a frequency detector to detect a fundamental frequency of the AC. The second oscillator may generate two substantially mutually orthogonal sinusoid signals having the selected frequency. The measuring device further may comprise a first group of multipliers that mixes the two sinusoid signals with a current and a voltage data signal of the AC respectively, a group of low-pass filters for removing high frequency components from the multiplication products, a second group of multipliers for mixing the filtered multiplication products respectively, and a plurality of adders each to sum together a pair of multiplication products of the second group of multipliers.

Abstract: Embodiments of the present disclosure may provide a charge redistribution DAC with two sets of capacitors that provides a DAC output by sharing charges between a plurality of pairs of capacitors in lieu of charging the capacitors using traditional external reference voltages. The charge redistribution DAC may comprise a plurality of pairs of first and second capacitors that each has a first side and a second side, and a group of first switches and a group of second switches. Each first or second switch selectively controls connection of the first side of a respective first or second capacitor to one of a pair of output signal lines according to a DAC input word. The charge redistribution DAC further may comprise a group of bridging switches each connected between second sides of paired first and second capacitors.

Abstract: Embodiments of the present invention provide a drive signal for a motor-driven mechanical system whose frequency distribution has zero (or near zero) energy at the expected resonant frequency of the mechanical system. The drive signal may be provided as a pair of steps sufficient to activate movement of the mechanical system and then park the mechanical system at a destination position. The steps are spaced in time so as to have substantially zero energy at an expected resonant frequency fR of the mechanical system. The drive signal may be filtered to broaden a zero-energy notch at the expected resonant frequency fR.

Abstract: A programmable compute unit with an internal register with a bit FIFO for executing Viterbi code is configured to accumulate in the forward path the best-path to each state in an internal register and store the survivor trace back information bit for each state in each stage in a bit FIFO; and in the trace back, selecting the optimal best-path through the Viterbi trellis by tracing through the bit trace back information survivor bits beginning with the survivor bit of the last stage path; and generating in response to the Viterbi constrain length and a current bit FIFO address, the next bit FIFO address and decoded output bit for the next previous stage.

Abstract: In a directional coupler having flaps on a pair transmission lines to be coupled, structural characteristics such as the distance between adjacent flaps, the length and width of a flap, the direction of projection of the flaps, and whether and to what degree the flaps on the two transmission lines overlap can be selected in order to optimize electrical characteristics of the coupler.

Abstract: An adaptive delay device that provides a delay to a signal based on circuit conditions such as temperature, supply voltage values and/or fabrication processes. The adaptive delay device may respond to circuit conditions by charging a capacitive device to a threshold voltage. A comparator may incorporate the adaptive delay device to provide adaptive timing for the comparator functions thereby attaining improved noise performance and/or reduce power consumption.

Abstract: Apparatus and methods for equalization are provided. In one embodiment, an apparatus for equalizing an input voltage includes a first capacitor and a first resistor having a first end and a second end, the first end configured to receive the input voltage. The apparatus further includes a second resistor having a first end electrically connected to the second end of the first resistor at an output node. The apparatus further includes an inverting voltage buffer for substantially inverting the input voltage to generate an inverted input voltage. The apparatus further includes a transconductance buffer for receiving the inverted input voltage and for generating a current from a first end of the first capacitor to the output node having a magnitude equal to about the magnitude of the input voltage signal divided by the impedance of the first capacitor.

Abstract: A pre-distortion circuit that may introduce a pre-distortion signal in a communication channel by determining a harmonic signal of the signal to be output. One or more image correction signals of the signal to be output may be determined. The one or more image correction signals may be complex conjugate signal variations of the signal to be output. The harmonic signal, the one or more image correction signals and the signal to be output may be combined into a combined output signal. The combined output signal may be transmitted to a digital-to-analog converter. The predistortion circuit may be implemented in a FPGA, an ASIC, a digital-to-analog converter, and/or a separate IC package.

Abstract: An integrated circuit configured to provide a microphone output signal, comprising: a preamplifier coupled to receive an input signal, generated by either a first microphone member or a second microphone member, where one of the members is movable relative to the other microphone member; a voltage pump to output a pumped voltage; and a low-pass filter coupled to filter the pumped voltage from the voltage pump and to provide a bias voltage to either microphone member.

Abstract: A bias-shaping circuit for adjusting power consumption in a frequency divider to a temperature-dependent minimum includes a temperature-dependent bias source for producing a temperature-dependent bias. The bias is combined with an input signal to create an output bias. The output bias changes in response to a change in temperature to compensate for at least a portion of a temperature-induced change in the frequency divider, thereby adjusting power consumption in the frequency divider to a temperature-dependent minimum.

Abstract: A charge pump circuit can include a first pair of transistors having connected sources and gates configured to receive a first pump signal and an inverse first pump signal and a second pair of transistors having connected drains and gates configured to receive a second pump signal and an inverse second pump signal, sources of the second pair of transistors being connected to drains of the first pair of transistors at first and second connection nodes, wherein the first and second pair of transistors are all of the same transistor type and provide an output current in response to the first and second pump signals. The charge pump circuit can also include a voltage stabilizer circuit connected to the second connection node and configured to regulate the second connection node to have a voltage within a predetermined range about a selectable voltage. Duty cycle stabilizers and control loops such as delay locked loops can include the charge pump circuit.

Abstract: Disclosed is a micro-electro-mechanical switch, including a substrate having a gate connection, a source connection, a drain connection and a switch structure, coupled to the substrate. The switch structure includes a beam member, an anchor and a hinge. The beam member having a length sufficient to overhang both the gate connection and the drain connection. The anchor coupling the switch structure to the substrate, the anchor having a width. The hinge coupling the beam member to the anchor at a respective position along the anchor's length, the hinge to flex in response to a charge differential established between the gate and the beam member. The switch structure having gaps between the substrate and the anchor in regions proximate to the hinges.

Abstract: A microchip has a bonding material that bonds a first substrate to a second substrate. The bonding material has, among other things, a rare earth metal and other material.

Abstract: A tracking module that tracks the operation of a digital-to-analog converter (DAC). The DAC tracking module may be included on-chip with a DAC, and be formed with similar circuit components as a DAC. The DAC tracking circuit may output a signal indicating that the DAC within a SAR ADC has settled to an approximate value during each bit conversion. A differential solution is also provided. Power may be optimized because optimal conversion speed may be achieved, and a comparator within the DAC may be turned off or placed in a standby mode at the end of bit conversions, and before the next conversion cycle in response to the signal output by the DAC tracking module.