Abstract: A system and method for scene change detection in a video sequence employing a randomly sub-sampled partition voting (RSPV) algorithm is provided. In the video sequence, a current frame is divided into a number of partitions. Each partition is randomly sub-sampled and a histogram of the pixel intensity values is built to determine whether the current partition differs from the corresponding partition in a reference frame. A bin-by-bin absolute histogram difference between a partition in the current frame and a co-located partition in the reference frame is calculated. The histogram difference is compared to an adaptive threshold. If the majority of the examined partitions has significant changes, a scene change is detected. The RSPV algorithm is motion-independent and characterized by a significantly reduced cost of memory access and computations.

Abstract: A data processing chip with a flexible timing system and method for supplying clocks to a digital data processing system useful for power conservation. A phase locked loop generates a master clock from which a core clock and a system clock are derived. The frequency of each of the core and system clocks is independently controllable relative to the master clock and can be changed on the fly with glitch free and jitter free operation. The data processing chip is well suited for use in hand held electronic devices where power management is a concern. Power can be saved by lowering the frequency of the core clock, even for short intervals of time.

Abstract: In one embodiment, an image sensor includes an area pixel array, column readout lines, and array readout lines, wherein the area pixel array includes columns of pixels, each including pixels of a first type, each column readout line is selectively coupled to outputs of the pixels of the first type that are included in a respective column of pixels, and each array readout line is selectively coupled to at least one of the first column readout lines. In another embodiment, an image sensor includes a pixel array, column readout lines, and array readout lines, wherein the pixel array includes a row of pixels which includes pixels of a first type, each column readout line is selectively coupled to an output of a respective pixel of the first type that is included in the row of pixels, and each array readout line is selectively coupled to at least one of the column readout lines.

Abstract: A method for deinterlacing an interlaced video signal is provided which employs a median single edge based line average field interpolation algorithm. The algorithm employs a median filter to determine whether motion occurred between scanning two fields of an interlaced frame and, based on the results, reconstructing intermediate lines in the display frame. The median performs a median computation by determining whether a target pixel value is a median value, rather than computing the median value and determining whether the target pixel value is equal to the computed median.

Abstract: Methods and apparatus are provided for achieving low latency for high priority tasks in digital processing systems. A digital signal processor includes a core processor and a level one memory. In some embodiments, a store buffer is configured to hold write information for the level one memory and for a level two memory. A write buffer is configured to hold write information, received from the store buffer, for the level two memory. The write buffer has a normal capacity and an excess capacity. A memory controller enables the excess capacity of the write buffer when a high priority task is being serviced and inhibits write access to the excess capacity of the write buffer when a high priority task is not being serviced. In other embodiments, the digital signal processor includes first and second fill buffers configured to hold read data in a fill operation. The memory controller steers low priority read data to the first fill buffer or the second fill buffer based on priority of the fill operation.

Abstract: A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; and first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses. The DMA controller further includes a prioritizer configured to map DMA requests from different DMA requesters to the peripheral channels in response to programmable mapping information.

Abstract: A translation loop modulator for a transmission circuit in a communication system includes an input modulation unit for receiving at least one input signal that is representative of information to be modulated. The input modulation unit also receives a feedback signal, produces an intermediate modulated signal responsive to the input signal and the feedback signal. The modulator also includes a comparator unit that receives the intermediate modulated signal and a reference signal, and produces an output transmission signal responsive to the intermediate modulated signal and the reference signal. The modulator also includes feedback circuitry that is coupled to the output transmission signal, and to the reference signal. The feedback circuitry is also coupled to the input modulation unit and produces the feedback signal responsive to the output transmission signal and the reference signal.

Abstract: A sample rate converter reduces the sampling rate of a signal by a fractional number U/D, where U represents an up-sampling rate and D represents a down-sampling rate. The converter comprises an input for receiving an input data stream at a first rate and an FIR filtering stage. The FIR filtering stage comprises a set of D polyphase filter branches, each branch including a set of filter coefficients which operate on a sample of the input signal. The converter also comprises a commutative switch which selectively connects a sample of the input data stream to one of the polyphase filter branches, the switch being arranged to skip every U?1 filter branches during a cycle through the filter branches. An output outputs an output data stream at a second data rate which is lower than the first data rate.

Abstract: A one terminal capacitor interface circuit for sensing the capacitance of a capacitor includes a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to the input common mode voltage, a switching circuit for charging the capacitor to a first voltage level in a first phase, connecting, in a second phase, the capacitor to one of the summing nodes of the differential amplifier to provide a first output change substantially representative of the difference between the first voltage level and the input common mode voltage, and also representative of the capacitor; charging the capacitor to a second voltage level in a third phase, and connecting, in a fourth phase, the capacitor to the other summing node of the differential amplifier to provide a second output change substantially representative of the difference between the second voltage level and the input common mode voltage, and also representative of the capacitor; the combined first

Abstract: A circuit for a high speed digital buffer has an active load circuit connected to an output of the digital buffer. The active load circuit loads the buffer output with an active inductance to reduce the RC time constant at the buffer output. The active load circuit may be based on two active devices connected to the buffer output so as to form a differential cascode circuit.

Abstract: Methods and structures are provided to enhance the linearity of amplifiers such as those which include a complementary common-collector amplifier stage. The methods and structures configure this stage so that each transistor of the stage drives an output port through a linearizing resistance. The methods and structures then control a bias current through the stage to substantially be the thermal voltage VT divided by twice the linearizing resistance.

Abstract: A group metering method (and system) for monitoring electrical energy consumption by a plurality of proximate users replaces multiple individual user-meters by a single electronic meter. A single computational engine computes consumed energy values by the users and deploys a single subsection set (display, real time clock, and non-volatile memory) which can be located on a PCB. The system, usable for single or three phase, may be located out of reach from the users to make it tamper proof. Individual ADCs obtain electrical current values (through current transformers,) of power consumed by individual users and cooperate with a single DSP to compute energy consumption by individual users, readable on a common display in round robin fashion. Differences between the sum of energy values consumed by the users and a consolidated energy reading beyond a known threshold are reported as possible user-tampering. Asynchronous communication ports communicate with display units and AMR modules.

Abstract: The invention provides a thermal sensor having a first and second temperature sensing elements each being formed on a thermally isolated table in a first substrate.

Abstract: The invention provides a sensor including a first sensor element formed in a first substrate and at least one optical element formed in a second substrate, the first and second substrates being configured relative to one another such that the second substrate forms a cap over the first sensor element, the at least one optical element being configured to guide incident radiation on the cap to the first sensor element. The sensor also includes a reference sensor element whose output can be used to reference the output of the first sensor element.

Abstract: Detecting the presence of an electric fan is described. A current sink circuit is coupled to a pulse width drive output of a fan control circuit. A logic state in a logic input buffer is defined based on current flow through the current sink. The logic state indicates if a fan is coupled to the pulse width drive output.

Abstract: A bond pad structure for an integrated circuit includes first and second active devices formed in a substrate, first and second buses above the first and second active devices, respectively, a bond pad above the first and second buses, first interconnections between the first and second active devices and the bond pad, and second interconnections between the first and second active devices and the first and second buses, respectively. The first active device may be at least one PMOS transistor, and the second active device may be at least one NMOS transistor. A guard band region may be formed in the substrate.

Abstract: An output stage interface circuit (1) comprises a main bipolar transistor (Q1) coupling a data output terminal (5) to a first rail (2) to which the positive of the power supply voltage (VDD) is applied, and a substrate diffusion isolated main NMOS transistor (MN1) coupling the data output terminal (5) to a second rail (3) which is held at ground. Control signals from a data control circuit (6) selectively operate the main bipolar transistor (Q1) and the main MOS transistor (MN1) for determining the logic high and low states of the data output terminal (5) during data output.

Abstract: A power supply monitoring circuit is provided that utilises an adaptive internal control of the refresh rates of capacitors to reduce the power requirements of the circuit. The circuit provides at an output a signal indicative of the level of the supply voltage relative to a predetermined reference voltage.

Abstract: An analog to digital converter having improved differential non-linearity is provided. The converter has a memory which is used to look up the actual weight or a weight error corresponding to the bits that have been kept as part of the SAR process to form an output correction value A part of this, for example a residue (the part following the decimal point in a decimal representation) is used to drive a correction DAC which causes a correction to be applied to the trial value presented to a comparator used by the ADC.

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.