Abstract: An I/Q imbalance compensation block of a RF receiver for compensating an imbalance between an in-phase component and a quadrature component of an RF signal is disclosed. The compensation block includes a conjugation block; an adaptive finite impulse response (FIR) filter; and an adder. The filter use filter coefficients iteratively updated at least partly in response to a compensated digital signal. The filter can have a complex number for at least one, but not all of filter taps, and real numbers for other filter taps. The filter can be provided with adaptation step sizes different from filter tap to filter tap. The filter can also be provided with an adaptation step size(s) varying over time. The filter can also be provided with an adaptation step size(s) divided by the square norm of the compensated signal.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: An I/Q imbalance compensation block of a RF receiver for compensating an imbalance between an in-phase component and a quadrature component of an RF signal is disclosed. The compensation block includes a conjugation block; an adaptive finite impulse response (FIR) filter; and an adder. The filter use filter coefficients iteratively updated at least partly in response to a compensated digital signal. The filter can have a complex number for at least one, but not all of filter taps, and real numbers for other filter taps. The filter can be provided with adaptation step sizes different from filter tap to filter tap. The filter can also be provided with an adaptation step size(s) varying over time. The filter can also be provided with an adaptation step size(s) divided by the square norm of the compensated signal.

Abstract: Improved thrashing aware and self configuring cache architectures that reduce cache thrashing without increasing cache size or degrading cache hit access time, for a DSP. In one example embodiment, this is accomplished by selectively caching only the instructions having a higher probability of recurrence to considerably reduce cache thrashing.

Abstract: A MEMS stiction testing method applies a first electrical signal to a MEMS device having two opposing surfaces to cause the two opposing surfaces to make physical contact. The two opposing surfaces produce a second electrical signal when in physical contact. The method then substantially mitigates the first electrical signal after detecting that the second electrical signal has reached a prescribed maximum value.

Abstract: A lever shifter is provided for receiving a signal in a first voltage domain and providing an output signal in a second voltage domain. The level shifter reduces propagation delay and power consumption by mitigating contention between NFETs and PFETs during signal propagation.

Abstract: A system and a method may include performing a coarse estimation to eliminate at least one direction from a set of edge candidate directions without directly evaluating each direction; performing a fine estimation to select a single direction as corresponding to an edge; and performing a directional interpolation as a function of the single selected direction to generate a pixel value for a pixel being interpolated.

Abstract: A method for dividing a frequency includes the steps of receiving a first signal having a first frequency as a clock input to a first digital counter and outputting a second signal as a clock input to a second digital counter having a higher counting capacity than the first counter. The output occurs when the first counter reaches a first number of count cycles. The method also includes generating a third signal having a high cycle and a low cycle, which are determined at least as a function of the first number of count cycles. Depending on a desired division ratio, the high and low cycles may also be a function of a second number of count cycles associated with the second counter. The third signal has a frequency lower than the first frequency.

Abstract: A system for a Class AB Amplifier output stage that includes a first push pull system connected to an output terminal including a first driving transistor coupled to the output terminal and a second push pull system connected to the output terminal including a second driving transistor coupled to the output terminal. The amplifier also includes a current mode amplifier where the current mode amplifier's output is coupled to the first driving transistor's gate. The amplifier further includes a pair of resistors, a first resistor coupled to a first input terminal of the current mode amplifier, a second resistor coupled to a second input terminal of the current mode amplifier and coupled to the second driving transistor.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: An array of acoustic transducing unit cells configured with an acoustic focus or a beam steering orientation. A variety of time delays between consecutively coupled acoustic transducing unit cells provides acoustic focus. In another configuration, a resistive signal path between adjacent acoustic transducing unit cells can be used to acoustically steer an acoustic beam in a direction non-normal to the top surface in which the array is disposed. In a further embodiment, a signal pad is made available at each end of the connections through an array of capacitive micromachined ultrasonic transducing unit cells.

Abstract: A MEMS microphone has a backplate, a diaphragm movable relative to the backplate, and a backside cavity adjacent to the backplate or the diaphragm. The backside cavity has sidewalls with at least one rib protruding inward toward a center of the backside cavity.

Abstract: An embodiment of a logarithmic circuit may include a logging transistor, a guard circuit arranged to force an input current into an input terminal of the logging transistor, and a positioning circuit arranged to maintain a voltage of the logging transistor. The guard and positioning circuits may include first and second feedback loops, respectively. Another embodiment of a logarithmic circuit may include a logging transistor arranged to generate a logarithmic output in response to an input current, and a feedback loop arranged to provide adaptive compensation to the logging transistor. The feedback loop may be arranged to provide compensation in response to the magnitude of the input current. Another embodiment of a logarithmic circuit may include first and second logging transistors having collectors arranged to receive input currents, and first and second feedback amplifier arranged to drive emitters of the logging transistors.

Abstract: A method of spatial domain video enhancement/up-scaling including transforming the video input from the temporal domain to a K×K matrix of spatial domain coefficients; multiplying each spatial domain coefficient by corresponding elements of a K×K enhancement matrix to obtain enhanced spatial domain coefficients; depositing the enhanced spatial domain coefficients in the upper left K×K corner of a zero padded 2K×2K inverse transform matrix and inversely transforming them to scale the enhanced spatial domain coefficients and convert them back to video output temporal domain elements and a method of spatial domain video enhancement/down-scaling including transforming the video input from the temporal domain to a 2K×2K matrix of spatial domain coefficients; multiplying the upper left K×K corner of the 2K×2K matrix of spatial domain coefficients by the corresponding elements of a K×K enhancement matrix to obtain enhanced spatial domain coefficients; inversely transforming the K×K enhanced spatial domain coefficien

Abstract: An input signal is applied to a ratiometric gain/attenuator circuit. A nulling circuit is arranged to null the input signal with an output from the ratiometric gain/attenuator circuit. The ratiometric gain/attenuator circuit may include a gain stage in series with a ratiometric attenuator. By implementing the attenuator ratiometrically, the gain may be compensated with reference to a ratio of component values. A limiting stage with an absolute reference may precede the gain stage, and a pair of detector cells may arranged at the inputs to the nulling circuit.

Abstract: A circuit system includes a first circuit for receiving an input signal, a second circuit for interfacing with a user, a signal path connecting the first circuit to the second circuit, the signal path including a first isolator and a second isolator serially connected to the first isolator, and a capacitance detector that detects a change in a combined capacitance of the first and second isolators as an indicator of a breakdown of one of the first and second isolators.

Abstract: Activation systems and methods initiate High-Definition Multimedia Interface (HDMI) communication between an HDMI source and an HDMI sink through an HDMI receptacle of the source. These systems and methods are especially suited for use with mobile sources that generally operate from a battery that cannot provide the +5V signal which the HDMI protocol requires sources to place on the +5V pin of their HDMI receptacles. These systems and methods automatically detect the insertion of an HDMI cable into the source's HDMI receptacle and subsequently generate and apply the required +5V signal to the +5V pin of the source's HDMI receptacle to initiate HDMI communication. Because they are directed to use in mobile sources, the embodiments are configured to minimize current drain.

Abstract: An integrated circuit may include a plurality of circuit sub-systems that include at least one converter circuit operating in respective critical phases and non-critical phases of operation, a clock distribution circuit that has an input for an externally-supplied clock signal that is active during the non-critical phases and inactive during the critical phases, and a clock generator to generate an internal clock signal to the converter circuit that is active when the external-supplied clock signal is inactive.

Abstract: Embodiments of the present invention may provide a clock and timing generation scheme for a video signal processor (e.g., a scaler), which enables fast switching between different input video standards without disturbing the output clock or timing. The scheme also may minimize the number of video frames that are dropped or repeated at the output. This may be achieved by locking the video's output timing to the input timing and also by utilizing a frame buffer to remove instantaneous discontinuities caused when an input is changed.