Abstract: An analog-to-digital converter of the successive-approximation type including a digital-to-analog converter (DAC) comprising a plurality of independently-switchable current sources producing identical currents and connected to respective junction points of an R-2R ladder network. The common ladder terminal is driven by an operational amplifier so that the potential of the common terminal tracks that of the ladder output terminal. The ladder common terminal is connected to a comparator together with a sense ground lead. The output of the comparator is directed to bit sequencer circuitry which controls the switching of the DAC current sources to effect a match between the analog input current and the ladder output current.

Abstract: A digital-to-analog converter of the type formed with a plurality of current source transistors arranged to carry different levels of current according to a predetermined weighting pattern, e.g., a binary weighting pattern. In the converter, a plurality of identically sized current source transistors carry the different levels of current and thus operate at different current densities with different base-to-emitter voltages subject to temperature drift. Stable emitter voltages, providing accurate levels of weighted current, are developed by means of resistances between the bases of successive current source transistors and a current source for developing across the interbase resistances a voltage linearly varying with absolute temperature, corresponding to the difference between base-to-emitter voltages of the successive current source transistors.

Abstract: A digital-to-analog converter comprising an IC switch module providing four switch transistors and associated switch-control buffering circuitry. The emitter areas of the switch transistors are binarily weighted to provide equal current densities. The IC substrate also is formed with a fifth transistor to serve as a reference transistor for adjusting the supply voltage as necessary to maintain constant current through the switch transistors. To construct a digital-to-analog converter having a high bit resolution, a number of such "quad" switch modules may be combined, for example in a printed circuit card assembly including a thin-film resistor module providing binarily-weighted resistors on a glass substrate to set the current levels through the switch transistors.

Abstract: A digital-to-analog converter having means to suppress the transient signals present at the output of the converter in response to a clock pulse synchronized with the transient signal. The clock pulse applies a forward bias to a pair of series-connected diodes which clamp the digital-to-analog converter output to ground. An integrator is connected to the converter output terminal to stabilize and filter the output signal while the terminal is clamped to ground.

Abstract: A transistor amplifier of the Darlington type, in which successive transistors have their collectors connected in common and in which the emitter of the first transistor is connected to the base of the second transistor, is characterized by a source of bias current for the first transistor which tends to suppress variations in transistor current gain and which permits the Darlington amplifier to operate in differential configurations with low offset voltage drift and low offset current drift. The bias current source is arranged to direct between the emitter of the first transistor and the emitter of the second transistor a bias current which is a predetermined fraction, e.g., one-tenth, of the collector current of the second transistor, thereby stabilizing the operation of the first transistor.

Abstract: A digital-to-analog converter comprising an IC switch module providing four switch transistors and associated switch-control buffering circuitry. The emitter areas of the switch transistors are binarily weighted to provide equal current densities. The IC substrate also is formed with a fifth transistor to serve as a reference transistor for adjusting the supply voltage as necessary to maintain constant current through the switch transistors. To construct a digital-to-analog converter having a high bit resolution, a number of such "quad" switch modules may be combined, for example in a printed circuit card assembly including a thin-film resistor module providing binarily-weighted resistors on a glass substrate to set the current levels through the switch transistors.

Abstract: An integrated-circuit 12-bit digital-to-analog converter comprising binarily-scaled constant-current sources with associated switch cells employing bipolar transistors to direct the bit currents either to a summing bus or to ground. The switch cells include a first differential transistor pair to translate a single-ended binary logic signal to double-ended (balanced) format, and a second, fully-balanced differential pair operated by the balanced logic signal to direct the bit current correspondingly. A bias-generating circuit maintains a constant collector-base voltage at the constant-current source. The threshold voltage for the logic signals can be set for TTL logic or, by pin-programming, for CMOS logic of either low-voltage or high-voltage type.

Abstract: An analog-to-digital converter of the ramp-integrator type utilizing a special technique to reduce errors due to offset voltages. In a pre-conversion cycle, the integrator first is ramped away from a datum level and then back to that level, by sequential application of opposite-polarity reference signals. A digital net offset error is thereby determined as the difference in clock time between (a) the total time of ramp-up-and-back and (b) a fixed time period set by a clock generator. During the subsequent conversion cycle, the integrator is ramped up by the unknown analog signal and then is ramped back by a reference signal. The time of ramp-up is controlled in accordance with the amount of previously-determined net offset error so as to provide error correction.In the embodiment disclosed, the ramp-up time during the pre-conversion cycle is set at k/2 clock pulses, and the digital offset error is the difference in clock pulse time between the return to datum level and a fixed time of k clock pulses.

Abstract: A digital-to-analog converter of the type formed with a plurality of current source transistors arranged to carry different levels of current according to a predetermined weighting pattern, e.g., a binary weighting pattern. In the converter, a plurality of identically sized current source transistors carry the different levels of current and thus operate at different current densities with different base-to-emitter voltages subject to temperature drift. Stable emitter voltages, providing accurate levels of weighted current, are developed by means of resistances between the bases of successive current source transistors and a current source for developing across the interbase resistances a voltage linearly varying with absolute temperature, corresponding to the difference between base-to-emitter voltages of the successive current source transistors.

Abstract: A digital-to-analog converter utilizing a set of high-speed current switches each comprising a buffer transistor and a switching transistor interconnected with a common resistor in such a fashion that the buffer transistor in the normal "off" state supplies the common resistor with a current of predetermined magnitude to bias the switching transistor to cut-off; a control pulse coupled through an input diode cuts off the buffer transistor, the bias at the switching transistor is thereby eliminated, and the switching transistor immediately conducts.