Abstract: A monlithic interface circuit for use with a linear variable differential transformer (LVDT) position transducer. The interface circuit includes a drive circuit for providing an excitation signal of selectable frequency and amplitude to the LVDT primary winding. The interface circuit further includes a decoder responsive to signals induced in the LVDT secondary windings for computing the position p of the LVDT core as a solution to the equation p=K(A-B)/(A+B), where A and B represent the signals induced in the primary winding and K is a constant scale factor. The decoder includes circuitry for rectifying and filtering the secondary signals, a charge balance loop responsive to the detected signals for providing a binary signal having a duty cycle representative of B/(A+B), and an output circuit responsive to the binary signal for providing the position output. The decoder provides excellent scale factor stability and linearity and is relatively insensitive to variations in primary drive amplitude.

Abstract: A current-source ladder digital-to-analog converter is compensated for temperature changes by making the total current running through the converter proportional to absolute temperature and by terminating the parallel transistor chain forming the current source ladder with a transistor whose emitter voltage is greater than the emitter voltage of the least significant bit current source transistor by 2(KT/q)ln 2 volts. The aformentioned voltage difference is achieved by making the emitter area of the termination transistor at least eight times the emitter area of the least significant bit transistor.

Abstract: The invention provides a monolithic Y-bit resistive-ladder type digital-to-analog converter (DAC) having a unity gain inverting operational amplifier as an input buffer to the resistive ladder segment of the DAC. The reference voltage is applied to the input buffer amplifier. Optional bipolar operation is provided by applying a non-inverted reference voltage to the output of the resistive ladder segment of the DAC through a scaled resistance. Analog ground current cancellation is provided by a secondary X-bit R-2R ladder (where X Y) with the non-inverted reference voltage applied to it. The secondary bit ladder is switched in parallel with the top X bits of the main ladder, thereby supplying or sinking roughly the same amount of current as the X most significant bits of the main resistive ladder, but with opposite sense.

Abstract: A ramp voltage generator which utilizes a simple resistance/capacitance charging circuit to generate a linear ramp voltage is reset by means of a shorting transistor connected across the capacitor. The shorting transistor is, in turn, controlled by the output of a flip-flop that responds to set and reset signals applied to the circuit. In order to decrease the overall reset time of the circuit and thereby increase the operational frequency, a current switch is provided which bypasses the flip-flop and immediately diverts current to the shorting transistor upon the application of a reset signal to the circuit.

Abstract: In a parallel (or "flash") type analog-to-digital converter (ADC), a decoding technique and apparatus. First, the output of every comparator is examined relative to its nearest neighbors. If, for comparator "n", the outputs of "neighboring" comparators "n+1" and "n-1" both are in a different state than the output of comparator "n", the output state of comparator "n" is reversed. That is, each group of three adjacent comparators (n-1, n and n+1) is examined and the output of the "center" comparator is "corrected" by substituting the majority state of the three comparators for the output of the "center" comparator (i.e., comparator "n"). Second, the zeroes-to-ones transition point is found in the thus-corrected outputs. Once the transition point is found, a conventional encoding produces a digital output word. Circuitry is provided for the efficient implementation of the method and for performing the method in an equivalent single step.

Abstract: A monolithic integrated circuit generates a programmable time delay under control of a digital work. The delay is generated by comparing a ramp signal to a threshold determined by the value of the digital word and appears as a time difference between a trigger pulse and a pulse generated when the value of the ramp voltage equals the value of the threshold voltage. The ramp voltage is generated by a simple resistance/capacitance charging circuit whose time constant can be adjusted by the user. The threshold voltage is set by a digital-to-analog converter (DAC) and resistor circuit which converts the digital control word into a variable voltage. In order to stabilize the device against changes in temperature and power supply variations, a voltage coupling circuit forces the threshold voltage to track changes in the ramp voltage caused by temperature and power supply variations.

Abstract: Process of making an IC chip with thin film resistors, and IC chips made by such process, wherein a chip substrate first is covered with layers of thin film and interconnect material (with an intermediate barrier layer if needed), such layers being etched away in predetermined regions in accordance with the metal interconnect pattern, the remaining layered material being aligned vertically, and thereafter, in a section of the remaining material, etching away the interconnect material (and barrier material if used) to expose the thin film material to form a thin film resistor which is self-aligned with the adjoining sections of interconnect conductors. The material in the predetermined regions may be etched by a dry-etch (plasma) or by a wet-etch.

Abstract: Non-uniform compressional, thermal dissipation and thermal expansion stresses in packaged chip devices are eliminated or substantially reduced by providing an aluminum attachment layer on the back side of wafers from which the chips themselves, to be mounted in the packaged chip devices, are produced. The aluminum-backed chips produced from such aluminum-backed wafers can be attached to cavities or tabs of packages such that essentially 100% attachment or bonding contact of the chip back side to the package is obtained when the chip is attached thereto with a gold eutectic preform material.

Abstract: A repetitive wave sample suited to monolithic integrated circuit fabrication, comprising a comparator followed by a master/slave latch feeding into an integrator. The inputs of the comparator are connected to (a) an unknown repetitive waveform having a known frequency and (b) the output of the integrator, which is provided to the comparator through a feedback loop. The master/slave latch is controlled by a clock pulse having a frequency equal to the frequency of the unknown waveform. The master latch is activated on the rising edge of the clock pulse while the slave latch is activated on the falling edge of the clock pulse. The integration performed on the output of the slave latch causes the output voltage of the integrator (i.e., the output of the circuit) to approach the point being sampled on the unknown input waveform. The output voltage will eventually settle to within a preset error range of the input point being sampled.

Abstract: A magnetometer having only a single coil winding for sensing the magnetic field along a single axis. Functionally, the invention comprises an oscillator, and means for measuring the duty cycle thereof. The oscillator uses a saturating inductor which also serves as the magnetic-field-sensing element. The inductor is driven with a position voltage and when the current through the inductor exceeds a value which indicates that the core is saturated, the driving voltage switches to an equal-magnitude negative value. This negative drive is maintained until the current again indicates the core to be saturated, at which point the driving voltages switches back to the positive value. With no externally applied field, the inductor current averages to a zero value and the duty cycle of the driving voltage is fifty percent. An externally applied field helps the core saturate in one direction and hinders it in the other, resulting in a change in average inductor current and drive duty cycle.

Abstract: A circuit which employs a pair of MOS transistors operating at equal gate and sources voltages, and nearly equal drain voltages, to produce an accurately ratioed current mirror. The gate voltage of the transistor pair is controlled by a simple current mirror operating at a small fraction of the total output. The latter current mirror also functions as a wideband negative impedance converter. A comparable bipolar circuit is also discussed.

Abstract: The invention provides a circuit which substantially cancels the input bias current of an operational amplifier having a cascoded NPN-PNP inmput stage. The compensation circuit comprises three transistors. A first NPN transistor is coupled to the input stage such that its collector is coupled to the positive voltage source of the operational amplifier and its emitter is coupled to the emitter of the dual-collector transistor of the input stage. The second transistor, a PNP transistor, has its base coupled to the base of the dual-collector transistor and its collector coupled to the bases of both of the NPN transistors of the input stage, which form the inputs of the operational amplifier. This PNP transistor's emitter is coupled to the collector of a third transistor which is a dual-collector PNP transistor. A third transistor has an emitter coupled to the positive voltage source of the operational amplifier and a base coupled to the base of the NPN transistor of the compensation circuitry.

Abstract: A 12-bit sub-ranging A/D converter which operates through four successive sub-ranging cycles with an 8:1 gain change between the cycles. The residue signal for each cycle is directed to a four-bit flash converter the output of which sets the latches for corresponding bit-current-sources of a DAC. The flash converter input circuit comprises identical residue and reference amplifiers driving symmetrical residue and reference networks for controlling the flash converter comparators. The DAC output for each cycle is compared with the analog input signal to produce a corresponding new residue signal. There are 15 bit-current-sources, three for the first cycle, and four for each of the last three cycles. The MSB of each group of four bit-current sources is an overlap bit having the same current weighting as the LSB of the preceding group.

Abstract: A multiport RAM register file adapted for flowing data directly from an input port to an output port and for simultaneously writing to a location in the register file. In addition to the RAM register, the apparatus includes (1) a first set of multiplexers between the input ports and the RAM, (2) a second set of multiplexers between the output of the RAM and the output ports and (3) logic for controlling the multiplexers and writing to the RAM. The input multiplexers are controlled by flow-through address comparators; the output multiplexers are controlled by read address comparators. The data at any input port of the register file may be written to any of the RAM data bit buses by selecting the input multiplexer appropriately. Because the bit buses are being driven, this data simultaneously may be passed to the RAM output just as if the RAM were being read--i.e., as a flow-through.

Abstract: A bipolar bandgap reference circuit employing three resistors of selected nominal resistance values and a method of trimming the values of two of the resistors to cancel the slope and curvature of output voltage due to thermal drift. One of the resistors provides a positive temperature coefficient to counter the temperature dependency of bipolar base-emitter characteristics; this resistor is not trimmed. The other two resistors are thin-film, low TC devices and are "trimmed" (i.e., adjusted) sequentially, to match calculated values intended to minimize the first and second derivatives of the bandgap cell output, as a function of temperature.

Abstract: An address generator for generating addresses for target locations in a circular buffer of length L, the buffer having an upper boundary and a lower boundary, the lower boundary being at an address which is a multiple of an integer power of two, and the address of a target location being offset by M locations from a current buffer location at address A, where M is no longer than L. The apparatus comprises a set of three registers, an adder for generating an absolute address, an adder/subtractor for generating a wrapped address which maps the absolute address into the buffer address space when the absolute address is outside that space, and certain control logic for selecting as the target address either the absolute address or the wrapped address. The contents of the three registers represent, respectively, the length of the buffer, the current address designated by the pointer, and the offset from the current buffer address to the target location in the buffer.

Abstract: In a microprogammed controller, the conventional pipeline register is replaced by a pair of coupled latches: a so-called "transparent" latch is placed between the output of the microprogram memory and the input of one or more system resources including at least the sequencer or address generator, and another latch is placed between the output of each such resource and the destination of its output. The appropriate bits of a microinstruction are supplied from the microinstruction memory to the associated resource via the transparent latch. The clock signal for the sequencer or other resource serves as the enable signal for the output latch (which can be either a transparent latch or an edge-triggered latch resposive to the rising edge of the clock signal), while the inverted sense of the clock signal provides the enable signal for the transparent latch.

Abstract: A circuit for controlling the circuit thresholds on an MOS integrated circuit takes advantage of the fact that all MOS devices of a particular type on the same chip have nearly identical characteristics. The circuit thresholds are varied by applying a control voltage to the back gate of an MOS device in each stage to be controlled. The control voltage is generated in a reference stage which utilizes a feedback loop to servo the back gate voltage of an MOS transistor in the loop. A reference voltage equal to the desired circuit threshold votlage is applied to the input of the reference stage. The reference voltage and the reference stage output are applied to an amplifier in the feedback loop. The amplifier applies to the back gate of the MOS transistor in the reference stage a control voltage that tends to equalize or establish a desired offset between the reference voltage and the reference stage output.

Abstract: A system for generating a continuous piece-wise linear approximating function that approximately corresponds to a predetermined function over a preselected domain, the approximating function having a selected number of linear segments, the approximating function at the endpoints of the domain falling on the predetermined function. The system first selects an initial error limit, then identifies the points which define the segments. In defining the segments, the system begins at a low endpoint, extends a test segment from the low point to a high endpoint on the predetermined function, and then tests the error between the test segment and the predetermined function at each point. If the error is less than the error limit, the system selects a new higher point on the predetermined function as the new high endpoint, and repeats the operation until the test segment error between it and the predetermined function by at most the error limit.

Abstract: A MOS sense amplifier having a differential input and a single-ended output, and formed of only six MOS transistors. The amplifier's non-inverting input is connected to the gates of first and second MOSFETs. The drains of the first and second MOSFETs are connected to each other and to the gates of third and fourth MOSFETs. The drain of the third MOSFET is connected to the sources of the second and sixth MOSFETs; and the source of the third MOSFET is connected to the positive supply voltage. The drain of the fourth MOSFET is connected to the sources of the first and fifth MOSFETs. The source of the fourth MOSFET is connected to ground. The inverting input of the sense amplifier is connected to the gates of the fifth and sixth MOSFETs. The drains of the fifth and sixth MOSFETs are connected to each other and provide the output terminus of the amplifier. The first, fourth and fifth MOSFETs are n-channel devices, while the second, third and sixth MOSFETs are p-channel devices.