Abstract: A pipelined multi-stage ADC in which residue signals are passed between stages as currents. All sample-and-hold circuits are designed to be current-in/current-out structures; all but one also provide a voltage output. A voltage representation of the analog signal is provided as input to the flash converter within the quantization loop of each stage, allowing implementation of a conventional voltage comparator architecture in the flash converter. An extra comparator is added to the flash converter and an extra segment is included in the DAC of each stage. Inputs above full scale and below zero can be converted and generate output codes. Whenever the input goes above full scale or below zero, an out-of-range bit is set and the digital outputs are set to all ones or all zeroes, respectively. The combination of out-of-range bit and digital codes tell whether overranging or underranging occurred.

Abstract: A three-terminal operational amplifier includes a current input, in addition to the conventional inverting and non-inverting inputs. The current input is inverted and added to the inverting input current, while its voltage is urged to a level equal to that of the inverting and non-inverting inputs. The new amplifier employs a pair of two-terminal operational amplifiers, the first of which has inverting and non-inverting inputs, and the second of which has the current input and a second input connected in common with an input to the first amplifier. Internal feedback circuits provide the desired current conveyance. The circuit may be implemented either with mutually discrete two-terminal operational amplifiers, or these elements may be merged into a single unified circuit. Applications include a general purpose adder/subtractor circuit, an inverting gain amplifier, an instrumentation amplifier, integrators and differentiators.

Abstract: A voltage-controlled delay is connected in series with a phase-locked loop. The voltage-controlled delay is controlled by the control voltage developed by the phase-locked loop amplifier and filter. With this arrangement, the amplifier and filter can be designed to have a transfer function that does not include an explicit zero. Consequently, the jitter transfer function of the overall structure can be designed to remain equal to or less than unity over all frequencies and jitter peaking is eliminated.

Abstract: High accuracy is achieved by employing, in conventional DAC architectures, very accurate current sources. To create these high-accuracy current sources, the outputs of several smaller, less accurate, nominally equal current sources are summed. A procedure is taught for selecting the number of current sources to achieve an arbitrary degree of accuracy with a desired level of confidence. Assuming the current sources are taken from a population whose output currents deviate from a design value according to a normal distribution, the minimum number of constituent current sources, n, required to provide an accurate total current is given by the formula n=(Z.sigma./E).sup.2, where Z is a number which corresponds to the probability that the output will fall within an error band E (i.e., a predetermined accuracy level) with a predetermined level of confidence, .sigma. is the standard deviation of the population.

Abstract: A signal conditioning circuit for an RTD includes feedback means to correct for the non-linear temperature characteristic of the RTD. The feedback means applies to the RTD a voltage which is a linear function of temperature, plus a fixed offset. The output signal from the circuit is proportional both to the RTD temperature and to the supply voltage. The resistors in the feedback system can be trimmed easily at a single temperature to calibrate the output. It can be combined with a metal film RTD on a single chip. The trimming can compensate for wide differences in RTD resistances.

Abstract: A phase-detector circuit for a phase-locked loop clock recovery system detects the phase difference between an information signal and a clock signal and produces a phase error signal representative of the phase difference. The phase detector includes, in one embodiment, five latches, serially interconnected, with the first latch receiving the information signal and each subsequent latch receiving the data output of the previous latch. The latches are enabled, in an alternating pattern, by the high-level and low-level portions of the clock signal. A first exclusive-OR (XOR) gate receives a delayed information signal and the data output of the second latch. A second XOR gate receives the data output of the second latch and the data output of the third latch. A third XOR gate receives the data output of the third latch and the data output of the fourth latch. A fourth XOR gate receives the data output of the fourth latch and the data output of the fifth latch.

Abstract: A multi-stage logarithmic converter of the "successive-detection" or "progressive-compression" type including circuitry providing an accurate, temperature-stabilized logarithmic transfer function. The gain stages are DC-coupled throughout, though each also employs a demodulator comprising a full-wave rectifier, allowing operation in both baseband and demodulating modes. The signal path is differential and is balanced, including the demodulators. Each gain stage is based on a differential amplifier, or "long-tail pair" operated in an open-loop mode and biased by a tail current generator which supplies a tail current that is both proportional to absolute temperature and compensated automatically for effects of finite transistor beta and base and emitter resistances. The demodulators are biased by a very low offset voltage which also is proportional to absolute temperature.

Abstract: A reference voltage distribution system for use on an integrated circuit to distribute, from a reference voltage input, to remote locations on the chip, precise images of the reference voltage. The system comprises (1) a reference buffer located proximate a reference input connection and (2) a plurality of remote generator blocks, one located at each of the remotely-located sub-blocks or circuits requiring an image of the reference voltage. The reference buffer generates from the reference voltage a number of precision currents, each proportional to the reference voltage. These precision currents are routed to the remote generator blocks. Each remote generator block converts its precision current into a precision reference voltage for local use. These latter reference voltages may be the same as or different from the reference voltage supplied to chip itself.

Abstract: A cascoded current mirror device is disclosed that is capable of producing an output current that is a direct function of an input current received by that device. The cascoded current mirror includes at least two portions connected together in a cascode manner. Provision is also made for feedback connection between those portions. This feedback connection can, for example, be a buffering connection. Voltage signals are generated by this device that can be used to drive and control additional output stages. Each such additional output stage is capable of producing an additional output current.

Abstract: An electric power measuring system wherein the current and voltage components are converted to respective digital signals which are multiplied and integrated to obtain a measurement of total power consumed. The current signal is developed by an A-to-D converter of the successive-approximation type, but differing from conventional such converters in employing two (or more) DACs in the feedback path where the analog feedback signal is developed for comparison with the analog current measurement signal. The two DACs are interconnected in such a way that the feedback signal is proportional to the square of the digital signal produced by the successive-approximation register (SAR). The final digital signal is developed by squaring the digital output of the SAR. The result is increased resolution at the low-level end of the scale, making it possible (in the particular embodiment) to achieve 1% accuracy at 1% of full scale, as well as 1% accuracy at 100% of full scale.

Abstract: A level shift circuit for converting an input signal referenced to a positive voltage to an output signal referenced to a lower voltage, such as ground. The level shift circuit includes one or more level shift stages and a reference current generator for causing a constant current to be drawn through each level shift stage. Each level shift stage includes a first transistor having a base for receiving the input signal and a collector connected to the positive voltage, a second transistor having an emitter coupled to ground, and a level shift resistor coupled between the emitter of the first transistor and the collector of the second transistor. The output signal from the collector of the second transistor is typically supplied to a TTL output stage. The reference current generator automatically compensates for temperature and power supply variations, so that the output of the level shift circuit tracks the threshold of the TTL output stage.

Abstract: A voltage coupling circuit for use in a digital-to-time converter insures that converter operation is stabilized against temperature and power supply variations. The digital-to-time converter operates by comparing a ramp voltage to a threshold voltage that is set in accordance with an input digital word. The voltage coupling circuit, which causes the ramp voltage to track changes in the threshold voltage, includes a current mirror arrangement that separates the voltage coupling and ramp generation functions. As a result, transistor base currents are not drawn through the ramp capacitor, and accuracy is improved in the case of long time delays.

Abstract: An auto-zeroing sample-hold amplifier capable of tracking an input voltage and, when designated, sampling and accurately holding an input voltage with no gain or offset errors includes input and output buffers with complementary, equal-magnitude offsets for minimizing offset voltage errors. An input voltage is sampled across a primary hold capacitor as well as a secondary hold capacitor [at the amplifier output to] in a sample mode. In a hold mode, the capacitors, in conjunction with the buffers and a transconductance amplifier, form a negative feedback loop around the transconductance amplifier to hold the sampled voltage and reduced voltage excursions at the output of the sample-hold amplifier. A special cancellation switch and capacitor are included for differentially cancelling voltage errors caused by switch charge feed-through onto the primary hold capacitor.

Abstract: A wet etching process wherein the etchant bath is ultrasonically vibrated, preferably while a carrier member holding the workpiece to be etched is slightly agitated. An apparatus for practicing the process includes a first vessel for holding a coupling fluid; a second vessel for holding an etchant solution; means for suspending the second vessel in the coupling fluid of the first vessel; and an ultrasonic generator means coupled to the first vessel to impart ultrasonic vibrations to the coupling fluid and, via the coupling fluid and second vessel, to the etchant solution.

Abstract: A flash converter in which an input circuit is provided for maintaining a substantially constant collector-base voltage on the input emitter-followers, so as to obviate the distortion caused by variation of the input capacitance with input voltage. The driving source directly drives the base of the emitter-followers and, through a level-shift circuit, also drives the collectors of the emitter-follower transistors.

Abstract: A differential amplifier including circuit means for generating a tail current which is not only porportional to absolute temperature, but also is adjusted to compensate for the non-ideal transistor geometries and properties, including finite beta and non-zero, temperature-dependent intrinsic resistances, so as to result in an amplification ratio which is substantially independent of all component variations.

Abstract: The invention comprises an n-bit analog-to-digital flash converter comprising 2.sup.n /2 input comparators, each having a first input coupled to receive the analog voltage to be converted and a second input coupled to a different reference voltage. The reference voltages of each consecutive input comparator are spaced apart two LSBs of the converter. Each input comparator has two output, OUT and an inverted version thereof, OUT. 2.sup.n -1 consecutive latches are provided. Every other latch receives at its inputs the OUT and OUT signals from a single associated input comparator. All other latches receive the OUT signal of one of the input comparators and the OUT signal of an adjacent input comparator.

Abstract: A delta modulator includes an integrator, a comparator for sensing the output of the integrator and a flip flop for synchronizing the comparator output to a clock signal and providing an error signal to the input of the integrator. The output of the delta modulator is a data stream having a time-averaged duty cycle that represents the input signal amplitude. The integrator includes an amplifier that is provided with positive feedback. Error caused by the finite open loop gain of the amplifier is cancelled by the positive feedback. As a result, high accuracy is achieved. The integrator amplifier is stabilized by the overall negative feedback of the delta modulator loop.

Abstract: The apparatus comprises a parallel analog-to-digital converter comprising a matrix of differentially coupled transistor pairs wherein the base of one transistor of each differential pair is coupled to a reference voltage and the base of the other transistor of each differential pair is coupled to the input voltage through a specified offset. In each row of differential pairs, the collectors of the transistors are alternately coupled to first and second row output points. The first and second row output points of each row are coupled to the inverting and non-inverting inputs, respectively of a comparator. Additional comparators are provided for comparing the second row output of each row with the first row output of the succeeding row. The matrix is arranged such that the combination of the comparator outputs is unique for each possible digital level in the full scale range of the converter. Logic circuitry is coupled to the comparator outputs to produce a computer usable code therefrom.

Abstract: A system for analyzing bone conditions, particularly (but not solely) for diagnosing osteoporosis and periodontal bone disease in humans. An ultrasonic signal (generally a pulse) having at least two components of distinguishable waveshape or frequency content in a range from about 100 kHz to about 3 MHz is launched transdermally into the patient, through a bony member such as the patella, and received at the other side. The transmission through the bony member and surrounding soft tissue varies in both amplitude and phase as a function of frequency, and the velocity of transmission varies between the bony member and the soft tissue. A variety of techniques are employed for analyzing the transmission of the ultrasonic signal to assess bone condition. These include at least: comparing the transit times through the bony member of energy in a first frequency range and energy in a second frequency; evaluating the transfer function through the bony member (i.e.