Abstract: A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.

Abstract: A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor.

Abstract: An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.

Abstract: An equalization scheme for a transmission line employs a Taylor series expansion which enables the provided equalization to be adjusted based on line length. Multiple circuit blocks compute respective terms of the Taylor series, which are then summed to provide a compensating frequency response. For example, for a conductor having a frequency response given by H(f)=e?kl(1+j)?{square root over (f)}, where k is a constant dependent on the physical parameters of the conductor, l is the length of the conductor and f is the frequency of the signal propagated via the conductor, the present scheme provides an inverse frequency response H?1 (f) given by H?1 (f)= 1 + kl ? f 1 ! + k 2 ? l 2 ? f 2 ! + k 3 ? l 3 ? f 2 3 ! + … . The kl terms serve as weighting factors which vary with the length of the conductor.

Abstract: An analog to digital converter comprising an Nth analog to digital converter and an N+1th analog to digital converter arranged in series such that a residue signal from the Nth analog to digital converter is provided as an input to the N+1th analog to digital converter, characterized in that a bandwidth control means is provided in a signal path for the residue signal and the bandwidth control means is controlled so as to have a first bandwidth during a first period following generation of a conversion result from the Nth analog to digital converter, and a second bandwidth less than the first bandwidth in a second period following the first period.

Abstract: Some embodiments provide real-time variable delays in a delay line. In some of these embodiments, the real-time variable delays may be enable without producing clock glitches. In an embodiment, delay cells in a delay line may be coupled together in a chain to form a lattice of inverters providing different paths of signal propagation. Each path may have a different number of inverters; each inverter adding a known processing time associated with the signal inversion process. In some embodiments, an input signal may be propagated in an inverted or non-inverted form to the inputs of multiple inverters in the lattice, including the inputs of inverters through which the input signal does not propagate. A desired delay time may be obtained in an embodiment by selecting a path containing a desired number and configuration of inverters. The path may be selected in an embodiment using switchably enabled inverters.

Abstract: A method for generating a data signal for synchronizing one or more electrically coupled digital receivers is disclosed. A data signal having a data rate is modulated with a pseudo-noise (PN) code having a data rate greater than the data rate of the data signal. The modulated data signal is demodulated by a receiver using the PN code. A correlation value is generated and is compared to a predetermined value to indicate phase synchronization. If the receiver is in phase synchronization with the transmitter, the received demodulated data signal is passed.

Abstract: A measuring apparatus including a self test function, the circuit comprising a capacitor; first to fourth switches; a test signal injector; at least one comparator having a signal input and a reference input the first switch being interposed between a first plate of the capacitor and a first input node, the second switch being interposed between a second plate of the capacitor and a second input node, the third switch being interposed between the first plate of the capacitor and the signal input of the comparator and the fourth switch being interposed between the second plate of the capacitor and a voltage reference, wherein the self test function comprises the steps of i) operating the signal injector to produce a first signal representative of an out of range voltage for an expected voltage difference between the first and second input nodes, and using the signal to cause the at least one comparator to place its output in an error state, and to charge the capacitor to the out of range voltage, ii) isolating

Abstract: A MEMS apparatus has a MEMS device sandwiched between a base and a circuit chip. The movable member of the MEMS device is attached at the side up against the circuit chip. The movable member may be mounted on a substrate of the MEMS device or formed directly on a passivation layer on the circuit chip. The circuit chip provides control signals to the MEMS device through wire bonds, vias through the MEMS device or a conductive path such as solder balls external to the MEMS device.

Abstract: A dynamically self-bootstrapping circuit for a switch features a resistor in series with the control node of the switch. A bypass switch connects a control node to ground. When the switch is in an off-state, the bypass switch is enabled.

Abstract: An interrupt-responsive non-volatile memory respond to an interrupt by aborting execution by a memory controller of a memory routine in a non-volatile memory, sets, a flag and executes an interrupt service routine; and upon completion of the interrupt service routine, in response to the flag, recovers the execution of the aborted memory routine.

Abstract: Methodology and circuitry for determining if a device, such as a cellular phone or personal digital assistant has been tapped is disclosed. The device includes an accelerometer and in response to an acceleration, the accelerometer outputs an acceleration signal. The accelerometer may continuously output an acceleration signal even if no acceleration occurs. A tap detection device receives the temporally sampled acceleration signal and takes the first derivative of the temporally sampled acceleration signal producing one or more derivative values. The tap detection system compares each derivative value to a threshold value and if the derivative value exceeds the threshold a tap is detected. By taking the derivative of the acceleration signal, the noise floor for the acceleration signal is reduced leading to more accurate results with less false positives and less positive negatives.

Abstract: A clock frequency divider for odd numbered divide ratios. The divider clocks two counters in parallel from a reference clock to be divided. One counter is loaded with the divide ratio and the other counter is loaded with the divide ratio except for the least significant bit. The second counter will set a latch when its count has elapsed. The first counter will reset the latch when its count has elapsed and will reload the counters. The latch is used for the divided output, but passes through a retiming circuit. The retiming circuit delays the output edge by one reference clock edge when the least significant bit indicates an odd numbered divide ratio.

Abstract: A most significant bits analog to digital converter for determining a first P bits of an N bit analog to digital conversion, the most significant bits analog to digital converter comprising: a digital to analog converter a capacitive attenuator, and a switching arrangement for inhibiting action of the attenuator during sampling and enabling the attenuator during conversion.

Abstract: An exemplary negative impedance converting circuit for functioning as a voltage buffer and/or negating the impedance of a connected load. The negative impedance converting circuit includes inputs, outputs, a first transconductance stage and a second transconductance stage. The transconductance gain value of the first transconductance stage is greater than a transconductance gain value of the second transconductance stage. Exemplary embodiments of a reference voltage buffer using the negative impedance converting circuit are also described.

Abstract: A PLL-based frequency translator provides a divider augmented with a sigma delta modulator (SDM) in a reference path. The system may include two primary functional blocks—an input PLL with its reference path containing an integer divider coupled with a SDM (a fractional frequency divider), and an output PLL with its feedback path containing an integer divider coupled with a SDM (a fractional frequency multiplier). The combination of an integer divider and an SDM yields a fractional divider that divides by N+F/M, where N is the integer portion of the division and F/M is the fractional portion of the division, with M denoting the fractional modulus. Furthermore, since it is desirable to have programmable division factors, it is beneficial to define N, F and M as integers as this simplifies a programming interface when the frequency translator is manufactured as an integrated circuit.

Abstract: A method and a device for canceling an offset voltage in an output of a comparator circuit include sampling a set of offset voltages; applying a set of correction voltages equal in magnitude and opposite in polarity to the set of offset voltages, the set of correction voltages being applied to an output generating arrangement of the comparator circuit; and enabling output of the output generating arrangement after the set of correction voltages is applied.

Abstract: A programmable clock booster system including a clock booster circuit including at least one boost capacitor connected between a first node and a second node for sampling an input voltage in a first phase and applying a boosting voltage to said second node during a second phase, and a programmable capacitor circuit connected to said first node for providing a programmable boosted voltage on said first node during said second phase.

Abstract: A method of transferring charge from a photosensitive array using a plurality of vertical shift registers, each having a plurality of vertical elements including first and last vertical element is disclosed The vertical shift registers are capable of transferring charge in a first direction from the first to the last vertical element The method also includes using at least one horizontal shift register having a plurality of horizontal elements. Each of the horizontal elements is arranged to receive charge transferred from the last vertical element of a respective one of the plurality of vertical shift registers, and shift the charge in a horizontal direction. The method includes operating the horizontal shift register during a plurality of horizontal operating intervals and operating the plurality of vertical shift registers during at least a portion of the plurality of horizontal operating intervals.

Abstract: A switched capacitor system with output glitch reduction step charges the switched capacitor by switching it to a first voltage level in a first phase, to an intermediate voltage level of a pre-charge node in a pre-charge phase and to the voltage level of the output node of the amplifier stage in a settling phase; the pre-charge node can be implemented at the input of the amplifier stage, the output of a preceding stage or at any other pre-existing suitable node in the amplifier system.