Abstract: A multi-voltage biasing system with over voltage protection has an amplifier with a stage including at least one output device and one cascode protection device having a predetermined maximum recommended voltage; a biasing network is selectively responsive to a plurality of different supply voltages at least one of which is higher than the maximum recommended voltage for providing to the stage a bias voltage to operate the cascode device and output device below their maximum recommended voltages.

Abstract: Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.

Abstract: A dual core crosspoint system includes a differential signal core for receiving N differential input channels with common mode voltage removed and providing m differential output channels with m output stages associated with the m output channels; and a common mode core for receiving N common mode voltage input channels derived from the N differential input channels and providing m common mode voltage output channels simultaneously with the m differential output channels.

Abstract: An apparatus and method is provided for optimizing LED driver efficiency. The present invention offers low cost solutions for powering LEDs while minimizing overall power dissipation in devices powered by a depletable power source. Low system cost is attained using a charge pump to increase LED drive voltage level and implementing combinations of drive techniques to overcome the inefficiency of the charge pump. A switch bypasses the charge pump when depletable power source output voltage is sufficient to directly drive an LED load. At certain output voltage levels, the switch can be opened causing the charge pump to boost drive voltage. The output voltage may also be PWM modulated to drive the LED load and, at some voltages, the depletable power source may drive the LED load directly. Efficiency levels of 90-97% are attainable.

Abstract: A system and method are provided to reduce the influence of parasitic capacitance at the drain and source of MOS transistors of a sampling circuit. In one embodiment, the bulk is left floating during a first phase and refreshed during a second phase. During the first phase, the effective parasitic contribution of the drain or source of a MOS transistor is lower due to the series combination of Cj and Cw capacitances. In another embodiment, a large resistance provides a path from a reference voltage to the bulk of a MOS transistor, thereby resulting in an effective parasitic capacitance of the series combination of Cj and Cw. Advantageously, the parasitic capacitance is reduced as well as its non-linear effect, the operating speed is improved, as well as the signal distortion and noise.

Abstract: A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer selects a channel for sampling, and a capacitive coupler capacitively couples the multiplexer to a sampling circuit. The sampling circuit produces sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data. A test circuit compares the sampled data with the data produced by the high-definition multimedia interface encoder.

Abstract: A system and method for setting analog circuit parameters requires providing a first set of data bits which represent the parameters to be set, deriving a first set of error correction bits from the values of the data bits in accordance with a predefined algorithm which enables the detection of at least one data bit error, receiving the data bits and error correction bits, deriving a second set of error correction bits from the values of the received bits in accordance with the predefined algorithm, comparing the first and second sets of error correction bits to detect the presence of data bit errors in the received data bits, correcting the data bit errors in the received data bits, and providing the corrected received data bits to the at least one analog circuit.

Abstract: A method for measuring active power of alternating current (AC) using a digital phase-locked loop (DPLL) includes the steps of (1) generating via the DPLL a pair of substantially mutually orthogonal sinusoid signals in response to an input voltage data signal, (2) mixing a first sinusoid signal of the pair with a current data signal of the alternating current via a first low-pass filter, (3) mixing the first sinusoid signal of the pair with a voltage signal of the alternating current via a second low-pass filter, and (4) computing an active power of the alternating current based on an output from the first low-pass filter and an output from the second low-pass filter.

Abstract: The invention is directed to an interface circuit for bridging voltage domains. The interface circuit receives an input signal, having a larger voltage domain, and safely provides the signal to an electronic device which has a smaller voltage domain. The interface circuit may include a transistor configured as a source follow so that an output of the transistor follows the input of the transistor. A blocking voltage may be provided at the input of the transistor to provide a voltage bias, blocking a range of input voltages to the transistor. The transistor may also have a blocking voltage at a drain terminal of the transistor, to block any output voltage above the blocking voltage.

Abstract: A system for converting an analog signal to a digital codeword having N bit positions that includes a dual DAC structure having a small DAC and a large DAC. At least one comparator is coupled to the small DAC and large DAC. The small DAC performs bit trials to calculate bit positions 1 to M, and the large DAC with performs bit trial calculates bit positions M+1 to N after having been set with bit decisions from the bit trials of the small DAC.

Abstract: An embodiment of a logarithmic circuit may include a logging transistor, a guard circuit arranged to force an input current into an input terminal of the logging transistor, and a positioning circuit arranged to maintain a voltage of the logging transistor. The guard and positioning circuits may include first and second feedback loops, respectively. Another embodiment of a logarithmic circuit may include a logging transistor arranged to generate a logarithmic output in response to an input current, and a feedback loop arranged to provide adaptive compensation to the logging transistor. The feedback loop may be arranged to provide compensation in response to the magnitude of the input current. Another embodiment of a logarithmic circuit may include first and second logging transistors having collectors arranged to receive input currents, and first and second feedback amplifier arranged to drive emitters of the logging transistors.

Abstract: An apparatus for generating a digital signal pattern may comprises a memory, a program sequencer, first and second circuits, and an event execution unit. The memory may have stored therein a plurality of instructions that, when executed, cause a digital signal pattern to be generated on a plurality of nodes. The program sequencer may be configured to control a sequence in which the plurality of instructions are retrieved from the memory and executed. The first circuit may sequentially step through a plurality of different output states in response to a clock signal. The second circuit may identify an output event when an output state of the first circuit corresponds to an output state identified by retrieved instructions of a particular type. The event execution unit may control states of signals on the plurality of nodes in a manner specified by the retrieved instructions of the particular type in response to the second circuit identifying an output event.

Abstract: A system for correcting duty cycle errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signals. A duty cycle error detector has inputs for a pair of amplified clock signals and an output for a duty cycle error correction signal. A signal conditioner is also provided with the differential amplifier having an input for the duty cycle error correction signal. Furthermore, the signal conditioner adjusts the differential clock signals in response to the duty cycle error correction signal. Also, a system for correcting cross point errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signal. A cross point error detector has inputs for a pair of amplified clock signals and an output for a cross point error correction signal. A signal conditioner is also provided with the differential amplifier having an input for the cross point error correction signal.

Abstract: The invention is directed to a circuit and method for equalizing digital interference. A digital interference equalizing circuit may include a signal clipping unit, receiving a digital signal and clipping the digital signal based upon a clipping function, and a dithering unit adding dither to the clipped digital signal. A digital interference equalizing circuit may also include a noise detection circuit, detecting the normal activity level in a digital signal which may then be used to scale the dither added to the digital signal.

Abstract: Devices and methods for varying individual periods or cycle times of upconverted clock signals within a corresponding reference clock cycle are disclosed. In some embodiments, these varying cycle times may improve signal synchronization between the upconverted clock and the reference clock. In different embodiments, different types of counters and counting circuits keep track of the number of elapsed upconverted clock cycles in order to determine the specific upconverted clock cycles with longer cycle times. In some embodiments, a signal may be sent to a delay line to change the amount of delay between upconverted clock pulses, thereby increasing or decreasing a specific upconverted clock cycle time or period. In some embodiments the specific upconverted clock cycle(s) changed in each reference clock cycle may vary, which may further improve reconciliation between the upconverted clock cycles and the corresponding reference clock cycle.

Abstract: Disclosed are apparatus and methods for electronic signal conversion in which a power level of the signal is used to adjust the bias current of a converter.

Abstract: In one embodiment, a configurable timing generator outputs at least one timing signal. The configurable timing generator comprises a first timing generator configurable to output the at least one timing signal so that the at least one timing signal is adaptable to a plurality of applications. In one embodiment, a configurable parameter storage unit comprising a parameter storage area configurable so as to store a plurality of parameters at least partially defining a desired plurality of waveform hierarchy elements, where the desired plurality of waveform hierarchy elements enable the definition of a waveform. In one embodiment, a method of constructing a waveform for a configurable timing generator, the method comprising acts of constructing a first pattern waveform, where the first pattern waveform comprises a first basic pulse, and constructing a first sequence waveform, where the first sequence waveform comprises a plurality of repetitions of the first pattern waveform.

Abstract: In various embodiments, the invention pertains to systems for acoustic beamforming that include one or more speaker membranes, such as, for example, a continuous ribbon membrane, and several independently addressable drivers. Moreover, certain embodiments relate to methods for beamforming with improved directionality.

Abstract: An analog amplifier includes at least one signal path. Each of the at least one signal path extends between an input and an output and includes a load device coupled to the output and a transistor coupled to the input. The analog amplifier further includes a dither current source selectively coupled to one of the at least one signal path. The dither current source is capable of supplying dither current to the load device of the selected signal path directly by bypassing the transistor of the selected signal path.

Abstract: Apparatus and methods for clock and data recovery are disclosed. In one embodiment, a clock and data recovery system includes a sampler, a deserializer, a phase detector and a frequency detector. The sampler may be configured to sample a serial data stream to produce data samples and transition samples. The deserializer may be configured to deserialize the data samples and the transition samples to produce deserialized data samples and deserialized transition samples. The deserialized data samples and the deserialized transition samples can be aligned and provided to the phase detector and the frequency detector, thereby improving phase alignment and cycle slip detection.