Abstract: Calibration methods and structures are provided for pipelined analog-to-digital converter systems. They are arranged to process samples of the digital codes with an algorithm that is preferably configured to repeatedly update an estimate of the transfer function with the difference between one of the input signals and the analog equivalent of the corresponding digital code. The calibration methods and structures are further configured to calibrate the transfer function of the converter stage wherein the samples are selected in accordance with various steps. These steps can include the step of injecting dither signals into a flash portion and an MDAC portion of the converter stage to thereby maintain dynamic range. They can also include the step of limiting the samples to those processed through a selected subrange of the subranges. They can further include the step of limiting the samples to those in which the absolute value of the input signals is less that 0.

Abstract: In one aspect, a level shifter for shifting a voltage level from a first voltage level to a second voltage level and having a predictable power-up state is provided. The level shifter comprises a first input and a second input forming a differential input to receive signals at the first voltage level, a first output and a second output forming a differential output to provide output signals at the second voltage level, and at least one circuit element coupled between the differential input and the differential output to pull the first output to a lower voltage level than the second output during power-up so that the level shifter powers-up in a desired state.

Abstract: Apparatus and methods are disclosed related to radio frequency (RF) power detection. One such apparatus includes a directional coupler, an RF switch, and an RF power detector. The RF switch can selectively change coupling between the directional coupler and the RF power detector. This can enable accurate power detection based on a ratio of power levels, without factory calibration or laser trimming.

Abstract: Apparatus and methods are disclosed related to phase synchronization in transmitters. One such apparatus includes a wireless transmitter with two or more separate and unrelated local oscillators. The apparatus can provide RF signals to multiple antenna elements, which can be implemented in systems such as beamforming systems or multiple input multiple output (MIMO) systems. A phase difference between local oscillators is determined using outputs of receivers. The phase difference can be used to adjust a phase of signals associated with one or more of the local oscillators, such that the phase of each signal provided to the multiple antenna elements can be aligned.

Abstract: A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor.

Abstract: A system, computer program product and method of obtaining a performance parameter associated with a sensor, such as an accelerometer, is provided. The method includes applying an acceleration to the accelerometer and a first frequency to obtain a sensitivity of the accelerometer at the first frequency. A first self-test is performed on the accelerometer. The first self-test includes stimulating the accelerometer with a first self-test stimulation signal encoded with the first frequency, such that the accelerometer outputs a first signal. A self-test equivalent acceleration is then determined based, at least in part, on the first signal and the accelerometer sensitivity at the first frequency. A second self-test is performed on the accelerometer. The second self-test includes stimulating the accelerometer with a second self-test stimulation signal encoded with the second frequency, such that the accelerometer outputs a second signal.

Abstract: A method for capping a MEMS wafer to form a hermetically sealed device. The method includes applying a glass bonding agent to the cap wafer and burning off organic material in the glass bonding agent. The cap wafer/glass bonding agent combination is then cleaned to reduce lead in the combination. The cleaning is preferably accomplished using an oxygen plasma. The MEMS device is coated with a WASA agent. The cap wafer is then bonded to the MEMS wafer by heating this combination in a capping gas atmosphere of hydrogen molecules in a gas such as nitrogen, argon or neon. This method of capping the MEMS wafer can reduce stiction in the MEMS device.

Abstract: Improved capacitive sensor operation is achieved with improved discrimination between environmental drift and apparent drift attributable to human proximity to the sensor. A proximity algorithm detects conditions interpreted as indicating a user is close to, but not touching, a sensor. When such proximity is detected, ambient value calibration is halted, thereby avoiding treating the human's proximity as environmental drift requiring compensation and preventing miscalculation of calibration. The proximity algorithm employs two moving-average filters (implemented in hardware or software) to monitor the CDC output values over time and to make appropriate adjustments to a signal representing the ambient, while distinguishing environmental drift from proximity-induced pseudo-drift.

Abstract: A method for calibrating a bandwidth of a phase-locked loop begins with detecting an error signal generated by the phase-locked loop in response to a stimulus signal. The difference between the integral of the error signal and a nominal value thereof is computed, and the bandwidth of the phase-locked loop is adjusted based on the computed difference.

Abstract: In various embodiments, the invention relates to semiconductor structures, such as planar MOS structures, suitable as voltage clamp devices. Additional doped regions formed in the structures may improve over-voltage protection characteristics.

Abstract: In one aspect, a method of reducing power consumption in a circuit by adaptive bias current generation of a bias current configured to bias, at least in part, at least one amplifier of the circuit is provided. The method comprises establishing the bias current based, at least in part, on a reference frequency of a reference clock providing a clock signal to at least one component of the circuit, and changing the bias current in response to a change in the reference frequency of the at least one reference clock, the bias current being change non-linearly with respect to the change in the reference frequency of the at least one reference clock. In another aspect, the method comprises establishing the bias current based, at least in part, on a capacitance of a reference capacitor, and changing the bias current in response to a change in the capacitance of the reference capacitor such that the bias current is changed non-linearly with respect to changes in the capacitance of the reference capacitor.

Abstract: A pipeline analog to digital converter comprising: a first analog to digital converter for determining a first part of an analog to digital conversion result, and for forming a residue signal; an amplifier for amplifying the residue signal, the amplifier including at least one offset sampling capacitor for sampling an offset of the amplifier, wherein at least one resistance is associated with the at least one capacitor so as to form a filter, and the at least one resistor is variable such that an amplifier bandwidth can be switched between a first bandwidth and a second bandwidth less than the first bandwidth during sampling of the offset.

Abstract: An improved technique that considerably reduces required logic and computational time for determining whether the difference between two multi-bit vectors is equal to a given number or lies between given two numbers in a digital logic circuit. In one example embodiment, this is accomplished by receiving a first N-bit vector A [N?1:0] and a second N-bit vector B[N?1:0] in the digital logic circuit, where N is a non-zero positive number. A third N-bit vector is then obtained by performing a bit-wise AND (A [N?1:0] & ˜B[N?1:0]) operation using A[N?1:0] and ˜B[N?1:0]. Further, a fourth N-bit vector is obtained by performing a bit-wise XOR (A[N?1:0]^˜B[N?1:0]) operation using A[N?1:0] and ˜B[N?1:0]. The difference between the first N-bit vector A[N?1:0] and the second N-bit vector B[N?1:0] is then declared as equal to a given number or to be within a given range of two numbers (+m and +n, m<n) based on bit patterns in the third N-bit vector and the fourth N-bit vector.

Abstract: An integrated circuit includes a micromachined transducer and a charge pump. More particularly, on one silicon substrate, a control circuit delivers high voltage from the charge pump to operate the transducer. An electronic apparatus, such as a cell phone or automatic test equipment may include such an integrated circuit.

Abstract: Embodiments of the present invention provide an apparatus and control method for an analog front end (AFE) amplifier for controlling DC restore operations. According to the exemplary method, a first input stage of the AFE is controlled to operate as a continuous time amplifier that has high input impedance and draws substantially no input leakage current for a first predetermined area of an imaging sensor image array. The first input stage is controlled to operate as a sample and hold amplifier with DC restore functionality for a second predetermined area of the imaging sensor image array. According to an embodiment, the AFE input stage operates as a continuous time amplifier when reading pixels from the sensor's active image array but operates as a sample and hold amplifier with DC restore when reading pixels from the image array that correspond to so-called ‘black-level’ pixels or pixels that otherwise fall outside the sensor's active image field.

Abstract: A sigma-delta converter suitable for measuring a photocurrent comprises an input node adapted to receive a current to be measured (Imeas), a capacitor connected to the input node, a clocked comparator coupled to the input node and to a reference voltage Vref at respective inputs, and a switchable current source connected to the input node which conducts a reference current Iref when switched on. The converter is arranged in a sigma-delta configuration, with the current source switched on to pull down the voltage (VCMP) at the input node when the comparator output toggles due to VCMP increasing above Vref, and to be switched off when the comparator output toggles due to VCMP falling below Vref, such that the comparator output comprises a digital bitstream which varies with Imeas.

Abstract: An input bias current cancellation circuit includes reference transistors placed in series and a current summation network. The current summation network can be configured to sum the base currents of the reference transistors to produce a summed current. A current mirror can be provided to attenuate the summed current to produce input bias cancellation currents. The input bias cancellation currents can be provided to the base inputs of an input bipolar differential pair, thereby reducing input current noise.

Abstract: Apparatus and methods for electronic circuit protection are disclosed. In one embodiment, an actively-controlled protection circuit includes a detector, a timer, a current source and a latch. The detector is configured to generate a detection signal when the detector determines that a transient signal satisfies a first signaling condition. The timer is configured to receive the detection signal, and to generate a current control signal. The current control signal is provided to a current source, which produces a trigger current at least partly in response to the control signal. The trigger current is provided to a node of the latch, thereby enhancing the conductivity modulation of the latch and selectively controlling the activation voltage of the latch.

Abstract: A serial protocol and interface for data transmission from a data transmitter 12 to a data receiver 14 where the propagation delay may be up to several clock cycles long and may be varying slowly. The data receiver provides a clock to the data transmitter. A synchronization signal provided by either the receiver or the transmitter initiates a frame of data transmission at a transfer rate controlled by the clock. The synchronization signal coordinates the transmission of a data header followed by a predetermined number of data bits, known as the frame length. The data receiver uses the header bits to determine the times to sample the subsequent data bits. The length of the frame is limited to provide sufficient likelihood the propagation delay line characteristics have not changed enough to cause a bit error. The system resynchronizes at the beginning of each frame.

Abstract: The present application relates to the manufacture of Wafer Level Chip Scale Packages (WLCSPs), which are a type of CSP in which the traditional wire bonding arrangements are dispensed with in favor of making direct contact by means of conductive bumps (typically solder balls) to the integrated circuitry. WLCSPs differ from fine pitch Ball Grid Array (BGA) and leadframe based Chip Scale Packages (CSPs) in that most of the packaging process steps are performed at wafer level. A package and method of manufacture are provided which prevent the ingress of light to the internal circuitry of WLCSP packages by providing a substantially opaque coating on the inactive side of the WLCSP packages and at least partially on the sides of WLCSP packages.