Abstract: A printed circuit balanced to unbalanced (balun) transformer. The balun includes strip circuitry having first, second and third conductors. The first conductor provides a primary inductor of the transformer. The primary inductor has a first electrode adapted for coupling to an unbalanced transmission line and a second electrode electrically connected to the ground plane conductor. The second conductor provides a first secondary inductor of the transformer. The first secondary inductor is inductively coupled to a first portion of the primary inductor. A first electrode of the first secondary inductor is electrically connected to the ground plane conductor and a second electrode of the first primary inductor coupled to a first of a pair of output ports. The conductor provides a second secondary inductor of the transformer. The second secondary inductor is inductively coupled to a second portion of the primary inductor.

Abstract: A method for forming an isolation wall in a silicon semiconductor substrate wherein a trench is etched into the silicon using a hard mask, a layer of silicon dioxide is formed on the side walls of the trench, a filling of polysilicon is placed in the region between the side wall layers, the polysilicon is planarized by etching while the hard mask remains in place, and the hard mask then is stripped from the silicon, permitting field oxide to be grown over the trench region.

Abstract: Emitter widths of 0.3 .mu.m on double polysilicon bipolar transistors are achieved using O.8 .mu.m photolithography and a double spacer process. The emitter width reduction is confirmed with structural and electrical measurements. The double-spacer device exhibits superior low current f.sub.T and f.sub.max.

Abstract: A data transmission system wherein a datastream of digital words is processed in two parallel pipelined datapaths with the logical operations being performed at a clock rate which is a fraction of some other clock rate identified as a main clock rate. The outputs of the datapath logic are directed respectively to T-latch storage registers the outputs of which are directed at the fractional clock rate to corresponding inputs of a multiplexer serving to combine the two datastreams into a single datastream at the main clock rate. The multiplexer is clocked in synchronism with the T-latch clocks in timed sequence to prevent the development of a transparent path between either T-latch input and the multiplexer output.

Abstract: A data transmission system wherein a datastream of digital words is processed in two parallel pipelined datapaths with the logical operations being performed at a clock rate which is a fraction of some other clock rate identified as a main clock rate. The outputs of the datapath logic are directed respectively to T-latch storage registers the outputs of which are directed at the fractional clock rate to corresponding inputs of a multiplexer serving to combine the two datastreams into a single datastream at the main clock rate. The multiplexer is clocked in synchronism with the T-latch clocks in timed sequence to prevent the development of a transparent path between either T-latch input and the multiplexer output.

Abstract: An integrated circuit chip for determining when the frequency of a clock pulse input signal is below a predetermined threshold level and including a capacitor charged up by a current source to produce a linearly-varying ramp signal. The charging circuit includes two MOS transistors, one arranged as a resistor to control the charging current, the other arranged as a capacitor to be charged. When the oxide layer produced by the IC process for making the chips varies in thickness from one batch of chips to a subsequently produced batch, the effect on the charging of the MOS capacitor resulting from the change in capacitance of the previously produced chip is at least partly compensated for by the corresponding change in resistance of the MOS resistor, thereby tending to maintain the charging rate constant.

Abstract: A voltage-to-frequency converter having an analog-to-digital converter, based on analog components, for converting samples of an analog signal into corresponding digital words and a digital-to-frequency converter, based on digital components, for converting the digital words into a train of pulses having a pulse repetition frequency related to the analog signal. With such an arrangement, the digital-to-frequency converter and the analog-to-digital converter are adapted to operate at different rates. Therefore, the analog-to-digital converter may be optimized at one operating rate while the digital-to-frequency converter is adapted to operate at a higher operating rate and over a wide range of operating rates. This arrangement thereby enables a slower, analog component based, analog-to-digital converter to be used fabricated with CMOS technology along with the higher, variable operating rate, digital component based, digital-to-frequency converter.

Abstract: Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, and novel chip made by such process. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transistor and also is implanted and diffused in the substrate to form a P-well for the sub-collector of an npn transistor. N-type material is then implanted and diffused into the P-well to form the npn sub-collector, and also is implanted in the substrate to form part of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer is grown over the N-type substrate. N-type material is implanted and diffused in the epi layer to complete the isolation wall for the pnp transistor, and to form the collector for the npn transistor. P-type and N-type material is implanted and diffused in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.

Abstract: An integrated-circuit (IC) chip formed with a D-to-A converter (DAC) and an amplifier to receive the DAC output and to produce a corresponding signal for an output terminal. The chip includes control circuitry to prevent harmful instability in the signal at the output terminal during times that one or more power supply voltages are changing. The control circuitry includes a voltage-monitoring device which produces a RESET signal when a monitored supply voltage is beyond its nominal operating range. The RESET signal de-activates the amplifier input and output circuits, and following a short time delay after the start of RESET, disables the amplifier by killing the amplifier bias currents. The chip is arranged to receive a RESET signal from external devices, and to produce a RESET signal for any other devices in the system.

Abstract: The yield of good die from wafers is optimized by positioning the first level mask with respect to the wafer in accordance with a calculated alignment relationship based on physical characteristics of the wafer and the size of the die to be formed in the wafer. The calculated alignment relationship establishes the offset between the wafer and the mask which will result in the maximum available die. This offset is calculated by a computer which examines a number of prospective offsets between the center of one of the die and the center of the wafer. The number of available die is calculated for each such offset, and the offset which maximizes the available die from the wafer is determined.

Abstract: An analog-to-digital (A/D) converter of the successive-approximation type wherein the digital-to-analog converter (DAC) includes a charge-redistribution, binary-weighted switched-capacitor array for producing the analog output for comparison with the analog input signal. A second switched-capacitor DAC is employed to develop error correction signals to be combined with the analog signal from the A/D conversion DAC. The conversion DAC array is connected to one input terminal of the comparator, and the error-correction DAC array is connected to the other comparator input terminal, an arrangement which reduces the number of capacitors required while providing symmetrical capacitance loading of the comparator input circuit.

Abstract: An IC chip having an analog-to-digital converter together with control circuitry for effecting switchover between normal-power mode and low-power mode. The control circuitry includes a first D-type flip-flop with reset which receives on its "D" input a continuous high signal; on its differential clock inputs the flip-flop receives complementary logic signals derived from the "conversion start" (CONVST) signal applied to one pin of an 8-pin chip. In normal mode, the CONVST signal is a short pulse having an initial negative-going (falling) leading edge, and the flip-flop responds to that leading edge by producing a high Q output (CONVEN). This signals the A/D converter to carry out a conversion. In low-power mode, the CONVST short pulse is positive. The subsequent negative-going (falling) trailing edge of the pulse activates the flip-flop to cause its Q output to go high and turn on the A/D converter.

Abstract: A digital-to-analog converter including a plurality of binarily-weighted stages each incorporating a differential switch-pair circuit which includes two matched bipolar switch transistors the bases of which are driven by a corresponding pair of complementarry signal sources. Two additional switches are included in this circuit, with each such switch being connected between a respective signal source and its corresponding transistor control electrode. These two switches are both opened before the clock-controlled activation of the complementary signal sources. A short time after such activation, sufficient to assure that the complementary signal voltages have stabilized at their new values, the two additional switches are reclosed simultaneously by a single control signal so as to effect synchronized switchover of the two switch transistors at that instant.

Abstract: A frequency-responsive integrated circuit (IC) for determining when the frequency of a clock pulse input signal is below a predetermined threshold level, the IC including a capacitor charged up at a nearly constant rate by a current source. If the capacitor voltage reaches one-third of the DC power voltage, and input pulses are received, the capacitor is discharged to start another charge-up cycle. If no input pulses were received, the capacitor continues to charge up until its voltage reaches two-thirds of the DC power voltage, at which point an output signal is produced indicating that the input frequency is below the predetermined threshold level.

Abstract: An ESD protective clamp device comprised of a two-terminal diode formed in an isolated chip cell. The lower part of this chip cell region contains a buried layer of silicon with P-type dopant, and the upper part is an epitaxial layer also with P-type dopant. An annular (ring-shaped) anode plug segment is formed at the outer reaches of the epitaxial layer with P+ doping. At the interior central region is an N-type plug circular in horizontal cross-section and concentric with the annular plug. This central plug serves as the cathode. Electrical connections are made to anode and cathode to provide interconnection with an IC circuit with a MOM capacitor to be protected.

Abstract: An integrated-circuit (IC) chip formed with a D/A converter (DAC) having a digitally-programmable circuit for setting the full-scale output range of the DAC by controlling its gain. The IC chip further includes analog sync level generator circuitry for driving computer graphics CRTs. The sync level generator circuitry is integrated with the DAC circuitry in such a way that the sync signal levels track changes made to the full-scale operating output range of the DAC and also track with changes in operating conditions such as varying temperature, supply voltage and RSET resistance in the DAC current control circuitry.

Abstract: An SOI/DI IC chip including a handle wafer in the form of a section of silicon substrate contiguous with the layer of insulation beneath the silicon slice containing the device regions separated by trenches filled with low-conductivity polysilicon dielectric. One of the trenches is etched through the layer of insulation, and the polysilicon in that trench is doped to provide desired electrical conductivity to establish electrical contact with the handle wafer. Metallization is applied over the top of this one trench to make possible electrical connection to the handle wafer from above the chip by use of conventional wiring techniques.

Abstract: A random access memory (RAM) having an array of memory cells the signal lines to which are activatable by corresponding current sources. The memory is divided into "pages", and control pulses are produced to turn on the current sources involved in activating the signal lines to any page of memory cells being accessed and to turn off the remainder. The control pulses are directed through a pipelined pair of registers, and a look-ahead logic circuit examines the two pipelined control pulses identified as the "present" and "next" pulses. This logic circuitry serves to turn on the current sources for the page of memory to be accessed during the next clock time, and to maintain in an on state the current sources for the page of memory presently being accessed.

Abstract: Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors. In this process an N-well is formed in a P-type substrate. P-type dopant is implanted in the N-well to become a sub-collector for a pnp transistor. N-type dopant is implanted in the substrate in a location laterally displaced from the N-well to become a sub-collector for an npn transistor. N-type material is implanted in the N-well to begin the formation of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer then is grown over the P-type substrate. N-type material is implanted in the epi layer to complete the isolation wall for the pnp transistor, and to complete the collector for the npn transistor. P-type and N-type material also is implanted in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.

Abstract: A random access memory (RAM) having an array of memory cells the signal lines to which are activatable by corresponding current sources. The memory is divided into "pages", and control pulses are produced to turn on the current sources involved in activating the signal lines to any page of memory cells being accessed and to turn off the remainder. The control pulses are directed through a pipelined pair of registers, and a look-ahead logic circuit examines the two pipelined control pulses identified as the "present" and "next" pulses. This logic circuitry serves to turn on the current sources for the page of memory to be accessed during the next clock time, and to maintain in an on state the current sources for the page of memory presently being accessed.