Abstract: A monolithic chip with an integrated circuit forming an 18-bit D/A converter powered by a single supply of +5 volts. The circuit includes a voltage reference producing two stable voltages of 3.5 V and 2.5 V which are directed to a control amplifier. This amplifier produces control signals for the current-source cells of a current-steering network utilizing a segmentation decoder for the three most significant bits, a collector-connected R/2R ladder for the intermediate bits, and an emitter-connected R/2R ladder for the remaining least significant bits. The control signals include one for setting the level of current through an NPN current-source transistor, a second for setting the level of current through a PMOS transistor for turning on or off a pair of switching transistors, and a third for establishing a bias voltage for the turn-on circuits for the NPN current-source transistor.

Abstract: An integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, is disclosed. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transistor and also is implanted and diffused in the substrate to form a P-well for the sub-collector of an npn transistor. N-type material is then implanted and diffused into the P-well to form the npn sub-collector, and also is implanted in the substrate to form part of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer is grown over the N-type substrate. N-type material is implanted and diffused in the epi layer to complete the isolation wall for the pnp transistor, and to form the collector for the npn transistor. P-type and N-type material is implanted and diffused in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.

Abstract: A technique for "marking" integrated-circuit (IC) chips so that, when large lots of the chips are drift-tested at different temperatues, each chip can be identified positively so as to be associated with the test data accumulated for the particular chip. The technique includes forming additional resistors on each IC chip with the resistors connected in series and to a voltage supply. The resistors are timmed at the wafer stage to produce at nodal points between the resistors voltages having magnitudes which uniquely identify each particular chip, thereby to permit part-identified tests to be performed after the chips have been packaged as parts ready for shipment.

Abstract: Wire-bonded IC chips are coated with siloxane polyimide and cured to a hardened state. The coating is applied over portions of the circuitry which are stress-sensitive. The coating is spaced away from the wire-bond regions of the chip. Thereafter, the coated chip is plastic encapsulated in conventional fashion.

Abstract: A monolithic chip with an integrated circuit forming an 18-bit D/A converter powered by a single supply of .+-.5 volts. The circuit includes a voltage reference producing two stable voltages of 3.5V and 2.5V which are directed to a control amplifier. This amplifier produces control signals for the current-source cells of a current-steering network utilizing a segmentation decoder for the three most significant bits, a collector-connected R/2R ladder for the intermediate bits, and an emitter-connected R/2R ladder for the remaining least significant bits. The control signals include one for setting the level of current through an NPN current-source transistor, a second for setting the level of current through a PMOS transistor for turning on or off a pair of switching transistors, and a third for establishing a bias voltage for the turn-on circuits for the NPN current-source transistor.

Abstract: Automatic test equipment (ATE) for post-production testing of multi-pin integrated circuits (ICs). Each pin is assigned to a pin card having a pin driver and an active load with the latter including both a current source and a current sink. The pin driver and active load are connectable alternatively to the IC pin in response to complementary inhibit signals. Within the active load, the source and sink and connected/disconnected by respective pairs of matched transistor switch circuits the individual switches of which are alternatively activatable by differential control means. Both switch circuits of each pair are supplied from a single current source. One switch circuit of each pair, when activated, directs the current from the single current source to (from) the IC pin, while the other switch circuit, when activated, directs the current to (from) a return line.

Abstract: A digital-to-analog converter comprising a set of identical DAC cells each including: (1) a PNP bipolar current source transistor producing a continuous output current (equal values for all DAC cells), (2) a pair of PMOS switches connected to the collector of the bipolar transistor to divert the output current to either a ground line or a corresponding node of an R/2R ladder, (3) ladder circuitry for maintaining the full-scale ladder voltage below a predetermined level which keeps the PMOS switches in the saturated region of their characteristics, and (4) make-before-break switch control circuitry to close the PMOS switch being activated prior to opening the other PMOS switch.

Abstract: A low-leakage-current JFET having electrically isolated top and bottom gates. The structure employs enclosed geometry wherein one source/drain region fully surrounds the other source/drain region. Connection to the top gate is made through a diffusion-barrier to prevent penetration of metallization into the top gate contact region. A non-penetrating contact layer is provided on the upper surface of the top gate so that the material of the contact layer does not enter the top gate region to any significant extent. Both the channel region and the shield layer are formed by ion-implantation.

Abstract: Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, and novel chip made by such process. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transistor and also is implanted and diffused in the substrate to form a P-well for the sub-collector of an npn transistor. N-type material is then implanted and diffused into the P-well to form the npn sub-collector, and also is implanted in the substrate to form part of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer is grown over the N-type substrate. N-type material is implanted and diffused in the epi layer to complete the isolation wall for the pnp transistor, and to form the collector for the npn transistor. P-type and N-type material is implanted and diffused in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.

Abstract: An integrated-circuit (IC) transimpedance amplifier having a successive series of DC-coupled balanced symmetrical amplifier stages with overall current feedback. The input stage includes a pair of series-connected NPN/PNP transistor with common emitters serving as the inverting input terminal. The second stage includes a cross-coupled transistor quad with the bases of the first quad pair coupled to the collectors of the first stage transistors. The inter-stage coupling circuit includes a series string of diodes connected between the collectors of the first stage transistor pair. The input stage transistor pair is identical to the transistor pairs of the second stage quad, and all of those transistors carry identical DC currents. An output stage amplifier is driven by a signal from the collectors of the first transistor pair of the second stage quad. The second transistor pair of the quad is coupled to the output stage through current mirrors to augment the output signal.

Abstract: An IC band-gap voltage reference including a pair of transistors having different emitter areas and driven by an amplifier feedback circuit to produce equal collector currents so as to develop an output voltage corresponding to the band-gap voltage. The amplifier output network includes a resistor network arranged to produce an output voltage which is a predetermined multiple of the band-gap voltage. The circuit provides for independent trimming of elements for adjusting the output voltage magnitude and its temperature coefficient.

Abstract: A 16-bit D/A converter formed on a single monolithic chip and having two cascaded stages each including a 256-R resistor string DAC. The analog output voltage of the first stage is coupled to the second stage by two buffer amplifiers each formed by a non-epitaxial process using a P-type substrate. The amplifiers include NMOS and PMOS-cascoded bipolar current sources arranged to avoid the use of metallization to provide for electrical interconnections within the source.

Abstract: Differentially-connected pairs of JFETs on an IC chip are protected from ESD events by connecting respective discharge control resistors to the drains of the JFETs in such a manner as to be in series with any flow of current through either JFET.

Abstract: An amplifier of the type having a differential input stage driving an active load which produces a single-ended output directed to a voltage-gain stage. The gain of the amplifier is isolated from the effects of load changes by a biasing circuit which forces the differential input stage to remain balanced at all times.

Abstract: A voltage-to-frequency converter comprising a triwave generator responsive to an input signal to produce an output triangular signal the frequency of which corresponds to the magnitude of the input signal, and a voltage-slope-to-periodic-function (VSTPF) generator which receives the output of the triwave generator and produces a pulsed output signal having a frequency which is a multiple of that of the triwave generator.

Abstract: A sample/hold amplifier comprising two transconductance stages with their inverting input terminals connected together. In sample mode, the input signal is connected to the non-inverting input of the first stage, and a hold capacitor is connected to the non-inverting input terminal of the second stage and driven by the amplifier output through a feedback circuit which forces the hold capacitor voltage to track the input signal. Upon switchover to hold mold, the roles of the two transconductance stages are interchanged: The non-inverting input terminal of the first stage is connected through a feedback circuit to the amplifier output, and the second stage receives as an input signal the voltage of the hold capacitor, which now is disconnected from the amplifier output. The net offset voltage developed on the hold capacitor is the difference between the respective offsets of the two transconductance stages.

Abstract: A new process making it possible to produce stable buried Zener diodes in large-sized wafers where slow ramping of diffusion temperatures is required to avoid crystal damage and other adverse effects. The process includes an initial deep ion implantation of p type dopant (boron). A second ion implantation of n type dopant (arsenic) is made over the p type implantation. Both implantations are driven in to the required degree. An additional p type dopant diffusion is made coincident with the base formation by ion implantation to establish connection to the original deep p-doped region, and an additional n type dopant diffusion is made coincident with the emitter formation to establish connection with the n type dopant implantation.

Abstract: An integrated-circuit analog-to-digital converter of the successive-approximation type formed on a single monolithic chip. The converter is made by a diffusion process wherein certain portions of the chip are formed with normal-mode linear transistors, and other portions are formed with inverted mode I.sup.2 L transistors. The normal-mode transistors provide a switchable current-source DAC, a set of three-state output buffers, and a comparator. The inverted mode transistors provide an internal clock and successive-approximation control circuitry for the DAC. The chip also includes a voltage reference to provide for absolute analog-to-digital conversions.

Abstract: An integrated-circuit analog-to-digital converter of the successive-approximation type formed on a single monolithic chip. The converter is made by a diffusion process wherein certain portions of the chip are formed with normal-mode linear transistors, and other portions are formed with inverted mode I.sup.2 L transistors. The normal-mode transistors provide a switchable current-source DAC, a set of three-state output buffers, and a comparator. The inverted mode transistors provide an internal clock and successive-approximation control circuitry for the DAC. The chip also includes a voltage reference to provide for absolute analog-to-digital conversions.

Abstract: A technique for enclosing microelectronic circuit elements in hermetically sealed packages comprising a planar ceramic substrate with a box-like ceramic cover sealed thereto by a fused glass coating. The glass sealant is applied to the substrate in the form of a paste which thereafter is fired at high temperature and cooled to produce a smooth glass coating. With the cover in place on the substrate, the glass coating is remelted by heat developed by infra-red radiation developed by four line-focussed radiant heaters at the four sides of the package. The radiation of each heater is focussed at the interface line between the cover and the substrate. Because the radiant heat is concentrated along the interface line, unwanted heat transfer into the package is minimized, and the temperature is prevented from rising sufficiently to damage heat-sensitive elements.