Abstract: An impedance in an electrochemical gas sensor can be measured by connecting at least one pin in an integrated circuit to at least one electrode in an electrochemical gas sensor, using a damping capacitor to connect the at least one pin in the integrated circuit to an electrical ground, applying a voltage to the electrochemical gas sensor to provide a bias voltage to at least one electrode in the electrochemical gas sensor, receiving a current from at least one electrode in the electrochemical gas sensor, determining a measured gas amount from the received current, activating a switch located within the integrated circuit to isolate the damping capacitor from the at least one pin in the integrated circuit, and measuring an impedance of the electrochemical gas sensor using an excitation signal while the at least one damping capacitor is isolated from the at least one electrode in the electrochemical gas sensor.

Abstract: A system current sensor module can accurately sense or measure system current flowing through a sense current resistor by shunting current through a gain-setting resistor and using an amplifier to measure a resulting voltage, with an output transistor controlled by the amplifier controlling current through the gain setting resistor in a manner that tends to keep the amplifier inputs at the same voltage. The resistors can be thermally coupled to maintain similar temperatures when a system current is flowing. The thermal coupling can include conducting heat from a first resistor layer carrying the current sense resistor to a thermal cage layer located beyond a second resistor layer carrying the gain-setting resistor. This preserves accuracy, including during aging.

Abstract: High speed, high dynamic range SAR ADC method and architecture. The SAR DAC comparison method can make fewer comparisons with less charge/fewer capacitors. The architecture makes use of a modified top plate switching (TPS) DAC technique and therefore achieves very high-speed operation. The present disclosure proffers a unique SAR ADC method of input and reference capacitor DAC switching. This benefits in higher dynamic range, no external decoupling capacitory requirement, wide common mode range and overall faster operation due to the absence of mini-ADC.

Abstract: Isolators for high frequency signals transmitted between two circuits configured to operate at different voltage domains are provided. The isolators may include resonators capable of operating at high frequencies with high bandwidth, high transfer efficiency, high isolation rating, and a small substrate footprint. In some embodiments, the isolators may operate at a frequency not less than 30 GHz, not less than 60 GHz, or between 20 GHz and 200 GHz, including any value or range of values within such range. The isolators may include isolator components galvanically isolated from and capacitively coupled to each other. The sizes and shapes of the isolator components may be configured to control the values of equivalent inductances and capacitances of the isolators to facilitate resonance in operation. The isolators are compatible to different fabrication processes including, for example, micro-fabrication and PCB manufacture processes.

Abstract: Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

Abstract: Systems and methods related to successive approximation register (SAR) analog-to-digital converters (ADCs) are provided. A method for performing successive approximation registers (SAR) analog-to-digital conversion includes comparing, using a comparator, a first digital-to-analog (DAC) output voltage to a sampled analog input voltage to generate a comparison result including a first positive output and a first negative output; and gating, using gating logic circuitry, at least one of the first positive output or the first negative output of the comparator to next logic circuitry, the gating based at least in part on a digital feedback comprising information associated with at least one of an opposite polarity of the first positive output or an opposite polarity of the first negative output.

Abstract: A reference electrode with a liquid-impermeable enclosure comprises a chamber for a reference electrolyte. The reference electrode also comprises a first electrode element comprises a reference electrolyte electrode surface arranged to contact a reference electrolyte located within the chamber and a second electrode element is provided at least partially outside the enclosure and comprises a sample electrode surface for contacting a sample. The first and second electrode are electrically connected through the enclosure. Alternatively or additionally, a conductive connecting element defining a part of the enclosure and/or extending through the enclosure electrically connects the first electrode element and the second electrode element.

Abstract: A switched power circuit to control a common-mode signal. The switched power circuit includes a first switch and a second switch configured to generate switch mode voltage between a first node and a second node. The switched power circuit further includes a feedback circuit that is configured to detect common-mode voltage generated between the first node and the second node by a first signal generated by the first switch and a second signal generated by the second switch, and incrementally adjust a timing parameter of the first signal to adjust the common-mode signal.

Abstract: A power device can be structured with a power switch having multiple arrangements such that the power switch can operate as a power switch with the capability to measure properties of the power switch. An example power device can comprise a main arrangement of transistor cells and a sensor arrangement of sensor transistor cells. The main arrangement can be structured to operate as a power switch, with the transistor cells of the main arrangement having control nodes connected in parallel to receive a common control signal. The sensor arrangement of sensor transistor cells can be structured to measure one or more parameters of the main arrangement, with the sensor transistor cells having sensor control nodes connected in parallel to receive a common sensor control signal. The sensor transistor cells can have a common transistor terminal shared with a common transistor terminal of the transistor cells of the main arrangement.

Abstract: A combination amplifier can include a “main amplifier circuit” for signal amplification, and a matching “compensation amplifier circuit” to monitor distortion in the main amplifier output signal. The compensation amplifier circuit provides a compensation signal to the main amplifier circuit to compensate for and servo out distortion therein. The compensation amplifier circuit includes a passive input network and an amplifier. The passive input network can connect to both the input and output nodes of the main amplifier circuit such that the input and output signals cancel within the passive input network, leaving only the low level distortion component introduced in the main amplifier. Thus, the compensation amplifier is then only operating on the low-level distortion introduced in the main amplifier to generate the compensation signal. Because the compensation amplifier is then only operating on the very low distortion signal, any distortion it introduces into the compensation signal is negligible.

Abstract: Radio Frequency (RF) systems configured to implement full-duplex wireless data transfer for rotary joints are disclosed. An example RF system includes a 60 GHz short distance communication link implemented using elliptically (e.g., circularly) polarized antennas. Such a system may provide a mm-wave, high-speed, wideband wireless communication link in a manner that is associated with simpler design and operation, mechanical integrity, and reduced power consumption, compared to alternative solutions.

Abstract: A reference signal generator circuit can be configured to provide a temperature-compensated voltage reference signal at an output node. The reference signal generator can include a diode-connected first FET device coupled between a supply node and the output node, and a flipped-gate transistor coupled between the output node and a reference node. The reference signal generator can include a bias current source configured to provide a bias current to the output node to adjust a current density in the flipped-gate transistor relative to a current density in the first transistor.

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.

Abstract: The disclosure relates to accurately determining a DC energy signal, such as a DC current or DC voltage, which may be particularly useful when controlling a formation/testing current of a battery cell during formation and/or testing. In the battery formation/testing context, a current sensor is used to measure the current of the battery cell, which is used as a feedback signal for controlling the current to achieve a target current. The transfer function of the current sensor is used to improve the accuracy of the current measurement. Because the transfer function can be regularly determined during formation/testing, a lower-cost current sensor with relatively poor temperature coefficient may be used. Any change in the gain of the current sensor may be detected by the transfer function determination and corrected for. Therefore, high current control accuracy may be achieved at lower cost.

Abstract: Systems, devices, and methods related to a sample rate converter (SRC) for implementing a rate conversion R are provided. The SRC receives input samples at an input rate Fin and outputs samples at an output rate Fout=Fin×R, where R is a fractional value greater than 1. The SRC includes a plurality of filters to process the received input samples and a multiplier-adder block to generate the output samples based on respective delta values and outputs of the plurality of filters. The SRC further includes a plurality of buffers to buffer samples between the plurality of filters and the multiplier-adder block based at least in part on N buffer read pointers, where N is an integer greater than 1. The SRC further includes resampler control circuitry to generate N delta values of the delta values and the N buffer read pointers in parallel based on R.

Abstract: High speed, high dynamic range SAR ADC method and architecture. The SAR DAC comparison method can make fewer comparisons with less charge/fewer capacitors. The architecture makes use of a modified top plate switching (TPS) DAC technique and therefore achieves very high-speed operation. The present disclosure proffers a unique SAR ADC method of input and reference capacitor DAC switching. This benefits in higher dynamic range, no external decoupling capacitory requirement, wide common mode range and overall faster operation due to the absence of mini-ADC.

Abstract: Example magnetic sensor system includes a magnet mounted on a rotatable shaft, and a magnetic sensing device in a vicinity of the magnet. The magnetic sensing device includes an angle sensor configured to detect an orientation of a magnetic field generated by the magnet as the rotatable shaft is rotated, a magnetic multi-turn sensor configured to detect a number of turns of the magnetic field generated by the magnet as the rotatable shaft is rotated, a magnetic disk mounted on the rotatable shaft, wherein the disk comprises at least a first track for inducing a change in a magnetic field generated by the magnetic disk, wherein the first track is formed from a plurality of curved segments distributed around the circumference of the magnetic disk, and a first incremental sensor configured to detect changes in the magnetic field induced by the first track as the rotatable shaft is rotated.

Abstract: An amplifier circuit comprises a first amplifier circuit stage including input devices connected to inputs of the amplifier circuit, a second amplifier circuit stage coupled to the first amplifier stage, a common mode extraction circuit configured to extract a DC common mode voltage of the first amplifier stage, and a bias circuit configured to bias one or more output devices of the second amplifier circuit stage using the DC common mode voltage.

Abstract: Passive gate bias network topologies are implemented for stacked FET switch structures, which improve the settling time and low cut-off frequency for both DC and non-DC operation. DC capable stacked switch bias structures provide gate and bulk bias voltages, using input DC voltages, which are coupled to the gate terminals and the bulk terminals of the stacked switches. The DC coupling can be achieved using resistors, or a combination of resistors and diodes. An exemplary SPST switch includes a series stacked switch in combination with a shunt stacked switch, which can be controlled between alternating states. For low cut-off frequency improvement structures, an input signal is coupled to the gate terminals and bulk terminals of the switches in the stacked switches, using a DC block capacitor and resistors. The low cut-off of the bulk can be improved by connecting the bulk terminal of one switch to the opposite polarity switch.

Abstract: This disclosure relates to monitoring the condition of electrical/electronic switches over time by monitoring the impedance of the switch. The condition of switches can degrade as they age, which can reduce their performance and may ultimately lead to failure. In many applications, particularly high-voltage applications, the reliable operation of switches may be very important and failures can present a safety risk and cause costly unscheduled system downtime for repairs. It has been realised that as the condition of switches change, their impedance changes, so monitoring the impedance can give a good indication of the condition of the switch, enabling potential faults/failures to be identified early and acted upon pre-emptively.