Abstract: One aspect of this disclosure is a transimpedance amplifier circuit with multiple resistive feedback loops can be implemented with multiple Kelvin sensing channels. A transimpedance amplifier and multiple Kelvin sensing channels can be implemented on a single die having multiple contacts, such as pins, for connecting multiple resistors to the Kelvin sensing channels. The Kelvin sensing channels can be implemented with T-junction switch networks in certain embodiments.

Abstract: A multilevel DC-DC converter includes a voltage source that provides a voltage Vout1 to at least one charge converter circuit and an output filter capacitor having an associated output voltage Vout2. The at least one charge converter circuit includes a transformer having at least one primary winding and at least two secondary windings, a primary and secondary circuit each having at least two switching elements, and a control unit which receives a control signal, such as but not limited to an envelope tracking signal, which represents a desired output voltage. The control unit is arranged to provide output control signals to the respective switching elements of the primary and secondary circuits to activate and deactivate the respective switching elements to obtain a desired output voltage Vout2. The multilevel DC-DC converter can be arranged to operate as a boost converter or as a buck-boost converter.

Abstract: A circuit, system, machine-readable storage medium and method for detecting the presence of a leakage path in a multi-cell voltage source is described. The system includes a detection circuit, the detection circuit having a first, second and third amplifiers, a first input of the first amplifier connected to a first terminal of the voltage source and the first input of the second amplifier connected to a second terminal of the voltage source, a second input of each of the first and second amplifiers connected to a reference capacitor, and an output of each of the first, second and third amplifiers connected to a respective first, second and third outputs of the detection circuit; and a processor having inputs connected to the first and second outputs of the detection circuit.

Abstract: An optical sensor module is disclosed. The optical sensor module can include a housing comprising an air cavity. An optical emitter die can be disposed in the air cavity of the housing. A top surface of the optical emitter die can face a first side of the housing, the optical emitter die configured to emit light towards the first side of the housing. An optical sensor die can be disposed in the air cavity of the housing adjacent the optical emitter die. The optical sensor die can be spaced from the optical emitter die by a lateral distance. A top surface of the optical sensor die can face the first side of the housing. There may be no septum between the optical sensor die and the optical emitter die that optically separates the optical sensor die and the optical emitter die.

Abstract: Apparatus and methods for control of the second order temperature dependence of the frequency of a mechanical resonating structure are described. The second order temperature dependence of frequency of the mechanical resonating structure may be non-linear. Control may be provided by doping of a semiconductor layer of the mechanical resonating structure.

Abstract: A dynamically tunable transconductor includes a voltage-to-current converter stage for generating a current signal based on a voltage signal; and a current scaling stage for scaling the current signal by a scaling factor to achieve a particular transconductance. Current scaling stage includes a coarse tune mechanism having an associated coarse tune step and a fine tune mechanism having an associated fine tune step, where the scaling factor is a ratio of the coarse tune step to the fine tune step. A delta-sigma modulator can implement the transconductor to generate loop filter coefficients by dynamically tuning the transconductance to achieve a particular resistance.

Abstract: A system implementing an MBIST device is disclosed. The system includes an ECC-protected memory and the MBIST device for self-test of the memory. The MBIST device includes a first access port communicatively connected to the memory via a first path, the first path excluding the ECC logic associated with the embedded memory, and a second access port communicatively connected to the memory via a second path, the second path including the ECC logic associated with the memory. The device is configured to test the memory, in a first mode of operation, via the first path and, in a second mode of operation, via the second path. One advantage of such system includes re-using, with little additional die area, of MBIST logic already required for manufacturing test of the product (first mode of operation) for system or application level tests that may be carried out by customers (second mode of operation).

Abstract: Existing synchronization methods can be inefficient in hardware-assisted implementations because of the effects of various jittery events. Thus, a method and an apparatus are provided to synchronize a slave device's clock to a master device's clock for a hardware-assisted implementation. The method can include the receipt of three messages. Time differences are determined based on a time extracted from two of the messages and a time of receipt of a different one of the messages. The slave device's clock can be adjusted based on these time differences. Thus, this method, which can include a dynamic weighted average to compute and implement the synchronization, can synchronize the clock of the slave device to the clock of the master device in a faster time interval.

Abstract: Reducing distortions in a digital-to-analog converter is a challenge for circuit designers. For current steering digital-to-analog converters (DACs), a quad switching scheme has been used to remove code-dependent glitching which is otherwise present in dual switching schemes. However, due to various impairments in the circuit, e.g., mismatches in the transistors, some code-dependent distortions remain even when a quad switching scheme is implemented. To address this issue, the quad switching scheme can be randomized to improve dynamic linearity while relaxing driving circuitry design and power constraints. Advantageously, randomization reduces the code dependency of the distortions and makes the distortions appear more noise-like at the output of the DAC.

Abstract: In an isolation system, different analog to digital converters (“ADCs”) are provided on a first side of an isolation barrier. Outputs from the ADCs may be merged into a common data stream and communicated across the isolation barrier by a single isolation device. The ADCs may sample independent signals or may sample a common signal. When the ADCs sample a common signal, the system may monitor the input signal for fault conditions. During no fault operation, results of an analog-to-digital conversion may be communicated across an isolation barrier by an isolation device. During a fault condition, data representing the fault condition may replace the ADC data in communication across the isolation barrier. Fault conditions may be signaled by unique data patterns that can be distinguished from ADC data.

Abstract: A MEMS switch has a base formed from a substrate with a top surface and an insulator layer formed on at least a portion of the top surface. Bonding material secures a cap to the base to form an interior chamber. The cap effectively forms an exterior region of the base that is exterior to the interior chamber. The MEMS switch also has a movable member (in the interior chamber) having a member contact portion, an internal contact (also in the interior chamber), and an exterior contact at the exterior region of the base. The contact portion of the movable member is configured to alternatively contact the interior contact. A conductor at least partially within the insulator layer electrically connects the interior contact and the exterior contact. The conductor is spaced from and electrically isolated from the bonding material securing the cap to the base.

Abstract: Embodiments of the present invention may provide a circuit. The circuit may include a primary side, a secondary side, and an isolated energy transfer device electrically isolating the primary side and the secondary side. The primary side may include a first energy storage device coupled to a power source, a control system coupled to the first energy storage device for power, a second energy storage device, and a coupling system, coupled to the control system, to selectively couple the second energy storage device to the power source in a first phase and to selectively couple the second energy storage device to the primary side of the isolated energy transfer device during a second phase.

Abstract: The present application relates generally to programmable impedances and employs an auxiliary impedance in parallel to a primary programmable impedance to augment the performance of the primary programmable impedance at lower impedance values.

Abstract: The system may include a pixel array, a selector, a sampler, and a converter. The pixel array may generate output signals representing radiation incident upon the pixel array. The selector may select one of the output signals. The sampler may sample the selected output signal. The converter may generate a digital signal based upon the selected output signal. The sampler may include a charge integrator that compensates for parasitic capacitance of the selector by selecting a first feedback capacitance to obtain a first sample, and after obtaining the first sample, selecting a second feedback capacitance to obtain a second sample. The first feedback capacitance may be greater than the second feedback capacitance.

Abstract: An exemplary timing generator includes a coarse delay circuit configured to generate a coarse delayed rising edge signal and a coarse delayed falling edge signal from a reference timing signal; a fine delay circuit configured to generate a fine delayed rising edge signal from the coarse delayed rising edge signal and a fine delayed falling edge signal from the coarse delayed falling edge signal; an edge combiner configured to generate the timing signal based on the fine delayed rising edge signal and the fine delayed falling edge signal; and a masking circuit configured to generate a rising edge masking signal and a falling edge masking signal for controlling when the rising edges and the falling edges of the timing signal are generated.

Abstract: A digital to analog converter (DAC) maps a digital word to an analog output. The DAC bits may have amplitude and timing errors. These errors (or sometimes referred herein as “non-idealities”) result in distortion and degradation of the dynamic range in DACs. To reduce these negative effects, delta-sigma patterns can be provided to two bit cells, a reference bit cell and a bit cell under calibration, to perform, e.g., amplitude calibration and timing skew calibration. Delta-sigma patterns are particularly advantageous over square wave signals, which cannot be scaled to perform amplitude calibration between bit cells having different bit weights and are limited in frequency to integer fractions of the sampling clock.

Abstract: Apparatus and methods for analog-to-digital conversion of quadrature receive signals are provided herein. In certain implementations, a transceiver system includes at least a first pair of analog-to-digital converters (ADCs) associated with a first quadrature receiver channel and a second pair of ADCs associated with a second quadrature receiver channel. The first and second pairs of ADCs can provide analog-to-digital conversion of the same receive signal, but can have different noise profiles relative to one another, such as a low pass noise profile and a band pass noise profile. The transceiver system can further include a reconstruction filter for combining the outputs of at least the first and second pairs of ADCs to generate output signals associated with a lower overall noise profile relative to that of either pair of ADCs alone.

Abstract: An apparatus comprises a switching circuit, an error amplifier circuit, a current threshold circuit, and an over-current detection circuit. The switching circuit provides a switching duty cycle that includes a charge portion and a discharge portion. The error amplifier circuit generates an error signal representative of a difference between a target voltage value and a voltage at an output of the voltage regulator circuit. The switching circuit adjusts the switching duty cycle to regulate the voltage at the output using the error signal and a reference waveform signal. The current threshold circuit generates an adaptive peak current limit threshold. The over-current detection circuit generates an over-current signal when the reference waveform signal satisfies the adaptive peak current limit threshold during the charging portion of the switching cycle. The switching circuit interrupts one or more switching cycles when the reference waveform signal satisfies the adaptive peak current limit threshold.

Abstract: An exemplary level shifter includes a clock level shifter configured to generate a level shifted clock signal from an input clock signal; and a switched capacitor logic controller coupled to the clock level shifter. The switched capacitor logic controller is configured to steer the level shifted clock signal based on a data signal and the input clock signal, providing a level shifted version of the data signal.

Abstract: The present application relates generally to programmable impedances and employs an auxiliary impedance in parallel to a primary programmable impedance to augment the performance of the primary programmable impedance at lower impedance values.