Abstract: A wireless network element is operably couplable to an antenna array for communicating with at least one remote wireless communication unit. The antenna array comprises a plurality of radiating elements where at least one first radiating element of the plurality of radiating elements is arranged to create a radiation pattern in a sector of a communication cell. The wireless network element comprises a receiver arranged to receive and process at least one signal from the at least one remote wireless communication unit via the at least one first radiating element. The wireless network element also comprises a beam scanning module for stepping/sweeping the radiation pattern through the sector of the communication cell, such that at least one signal from the at least one remote wireless communication unit is processed to identify signal parameters representative of incoming signal power and angle of arrival of the received at least one signal.

Abstract: A circuit, system, machine-readable storage medium and method for detecting the leakage impedance in a voltage source is described. The method for identifying a presence of a leakage path in a multi-cell floating voltage source may include supplying a current to a node of the floating voltage source and sampling the voltage of the floating voltage source using a pair of amplifiers connecting in inverting configurations. The method may include sampling a reference ground potential using a reference amplifier connected in an inverting configuration. Each of the amplifiers may output an output signal. The method may include adjusting the current supplied to the node of the floating voltage source and resampling the voltage of the floating voltage source and the reference ground potential. The value of the leakage impedance may be calculated using the sampled and resampled values. The measurements may be performed independent of the battery voltage.

Abstract: A die is packaged by flip-chip mounting the die with the active side facing a low loss substrate. A ground plane is coupled to the active side of the die by vias through the low loss substrate. The ground plane is positioned to concentrate high frequency electromagnetic fields in the low loss substrate. A tuning height can be adjusted to tune the center frequency of a circuit in the die.

Abstract: An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.

Abstract: Existing synchronization methods can be inefficient in hardware-assisted implementations because of the effects of various jittery events. Thus, a method and an apparatus are provided to synchronize a slave device's clock to a master device's clock for a hardware-assisted implementation. The method can include the receipt of three messages. Time differences are determined based on a time extracted from two of the messages and a time of receipt of a different one of the messages. The slave device's clock can be adjusted based on these time differences. Thus, this method, which can include a dynamic weighted average to compute and implement the synchronization, can synchronize the clock of the slave device to the clock of the master device in a faster time interval.

Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

Abstract: Heart rate monitors are plagued by noisy photoplethysmography (PPG) data, which makes it difficult for the monitors to output a consistently accurate heart rate reading. Noise is often caused by motion. Using known methods for processing accelerometer readings that measure movement to filter out some of this noise may help, but not always. The present disclosure describes an improved filtering approach, referred to herein as an iterative frequency-domain mask estimation technique, based on using frequency-domain representation (e.g. STFT) of PPG data and accelerometer data for each accelerometer channel to generate filters for filtering the PPG signal from motion-related artifacts prior to tracking frequency of the heartbeat (heart rate). Implementing this technique leads to more accurate heart rate measurements.

Abstract: Embodiments of the present invention may provide a battery monitor for a battery system that avoids current loops. A battery monitor may be provisioned as an integrated circuit and may include a pair of supply pins for reception of power to the integrated circuit, a third high impedance pin, and a voltage regulation circuit. When the circuits are deployed, the supply pins of several battery monitors may be connected to each other to form a stack. The high impedance inputs of each battery monitor may be coupled to low voltage terminals of an associated battery cell. A voltage reference circuit within the battery monitor may maintain the voltage at a low voltage supply of the monitors at a level that matches the voltage present on the high impedance input. Thus, the voltages on the monitors' low voltage supplies may be regulated. As a result, no current should flow through the high impedance pins of the battery monitor.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: The present invention relates in one aspect to a DC linear voltage regulator circuit for generating a regulated DC output voltage based on a DC input voltage. The DC linear voltage regulator circuit comprises a DMOS pass transistor comprising drain, gate, source and bulk terminals wherein the drain terminal is connected to a regulator output which is configured to supply the regulated DC output voltage and the source terminal is connected to a regulator input for receipt of the DC input voltage. The DC linear voltage regulator circuit comprises a switchable leakage prevention circuit, connected to the bulk terminal of the DMOS pass transistor, and configured to automatically detect and interrupt a flow of leakage current from the regulator output to the bulk terminal.

Abstract: A serial peripheral interface (SPI) host port is disclosed that enables a host external to a processor to access the processor's memory-mapped resources using SPI memory command protocol. An exemplary processor can include a system interconnect connected to memory-mapped resources and a SPI host port connected to the system interconnect. The SPI host port is configured to use SPI memory command protocol to access memory-mapped resources of the processor for the host external to the processor.

Abstract: Disclosed herein are systems for calibrating an analog-to-digital converter (ADC) device, as well as related devices and methods. In some embodiments, a system for calibrating an ADC device may include an ADC device, wherein the ADC device includes an ADC and a dither source, and wherein the ADC device is to apply a set of calibration parameters to generate digital outputs. The system may also include calibration circuitry, coupled to the ADC device, to determine which of multiple sets of values of calibration parameters results in the digital outputs having the lowest amount of noise, and to cause the ADC device to apply the calibration parameters associated with the lowest noise.

Abstract: A system, such as a system-on-chip, has a non-debug domain and a debug domain. The debug domain has a debug framework that enables a debugger driven, non-debug domain system reset. The system includes a reset control unit, and a debug trigger mechanism that includes a debug trigger interface (DTI) connected to the reset control unit. The DTI is configured to trigger the reset control unit to reset the non-debug domain. The DTI may further be configured to monitor a status of the non-debug domain system reset.

Abstract: An accelerometer or other motion sensor is used to provide power to an entire processor system such that the processor does not need to be powered to process the motion signals for initial power-on control. After the processor system is powered on, the processor system may receive and process motion signals as normal, including, for example, performing various power-control functions such as power-down of certain components or the entire system upon detection of a lack of motion for a predetermined amount of time.

Abstract: Speakers do not always operate linearly. Linearity of the speaker can affect the quality of the sound produced by the speaker, i.e., causing distortions in the sound, if the nonlinearites are not accounted for. To determine nonlinearities of the speaker, the speaker is often modeled and measurements are made to estimate the characteristics of the speaker based on the model. By using an angle sensor and a light source, a speaker manager can make a direct measurement of excursion or displacement of the speaker. Moreover, when the angle sensor, the light source, and the light beam are configured appropriately with respect to the moving cone of the speaker, the measurement can be substantially linear with respect to the amount of excursion or displacement. Such measurements are far simpler to use and in some cases more accurate than measurements made by other types of systems.

Abstract: Image capturing systems with interline CCD structures designed to reduce the delay between captures of subsequent image frames are disclosed. Proposed interline CCD structures include two or more sets of storage units associated with a given set of photodetecting elements, where each photodetecting element is associated with one storage unit of each set of storage units in that the charge generated by the photodetecting element during the acquisition of a particular image frame (i.e. during a particular exposure period) may be stored any one of these storage units prior to read-out. Providing multiple sets of storage units allows read-out of charge corresponding to one image frame and stored in one set of storage units while accumulating charge corresponding to another image frame in another set of storage units, thus reducing the delay between captures of different image frames. Consequently, errors and artifacts of the image capturing system can be minimized.

Abstract: The present disclosure provides a feedback control system and method for a bidirectional VCM. The system employs an analog core that is common to both the PWM and linear modes of operation. The analog core includes a feedback mechanism that determines the error in the current flowing through the motor. The feedback mechanism produces an error voltage that corresponds to the current error, and applies the voltage to a control driver. The control driver then controls the motor, based on the error voltage, in either a PWM or linear mode. By sharing a common core, the switching time between modes is improved. Furthermore, the output current error between modes is reduced.

Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.

Abstract: A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period.