Abstract: Embodiments of the present invention may provide a receiver. The receiver may include an RF section and a quadrature mixture, coupled to the RF section, to downconvert a first group of wireless signals directly to baseband frequency quadrature signals and to downconvert a second group of wireless signals to intermediate frequency quadrature signals. The receiver may also include a pair of analog-to-digital converters (ADCs) to convert the downconverted quadrature signals to corresponding digital quadrature signals. Further, the receiver may include a digital section having two paths to perform signal processing on the digital baseband frequency quadrature signals and to downconvert the digital intermediate frequency signals to baseband cancelling a third order harmonic distortion therein. The receiver may be provided on a monolithically integrated circuit.

Abstract: A microprocessor circuit may include a software programmable microprocessor core and a data memory accessible via a data memory bus. The data memory may include sets of configuration data structured according to respective predetermined data structure specifications for configurable math hardware accelerators, and sets of input data for configurable math hardware accelerators, each configured to apply a predetermined signal processing function to the set of input data according to received configuration data. A configuration controller is coupled to the data memory via the data memory bus and to the configurable math hardware accelerators. The configuration controller may fetch the configuration data for each math hardware accelerator from the data memory and translate the configuration data.

Abstract: The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: A method of forming a MEMS device provides first and second wafers, where at least one of the first and second wafers has a two-dimensional array of MEMS devices. The method deposits a layer of first germanium onto the first wafer, and a layer of aluminum-germanium alloy onto the second wafer. To deposit the alloy, the method deposits a layer of aluminum onto the second wafer and then a layer of second germanium to the second wafer. Specifically, the layer of second germanium is deposited on the layer of aluminum. Next, the method brings the first wafer into contact with the second wafer so that the first germanium in the aluminum-germanium alloy contacts the second germanium. The wafers then are heated when the first and second germanium are in contact, and cooled to form a plurality of conductive hermetic seal rings about the plurality of the MEMS devices.

Abstract: Apparatus and methods for active detection, timing, and protection related to transient electrical events are disclosed. A detection circuit can generate a first activation signal in response to a transient electrical stress event across a first node and a second node. A blocking circuit is configured to bias the base of a first driver bipolar transistor to slow down discharge of accumulated base charge of a first driver bipolar transistor, which permits the first driver bipolar transistor to remain activated for a longer period of time than had the base of the first driver bipolar transistor been biased to the same voltage as the emitter of the first bipolar transistor. Shut-off circuitry can be included in some embodiments to prevent a discharge circuit from activating during normal operating conditions.

Abstract: Apparatus and method for digital configuration of integrated circuits (ICs) are provided herein. In certain implementations, an IC includes an impedance sensing circuit and at least one pin used for digital configuration. The impedance sensing circuit can detect an impedance value of an external passive network electrically connected to the pin, and can digitally configure the IC based on the detected impedance. For example, an end-user can connect an external resistor of a particular resistance to the pin, and the impedance sensing circuit can sense or detect the external resistor's resistance and digitally configure the IC based on the detected resistance. Accordingly, an end-user can digitally configure the IC by connecting a passive external component corresponding to a desired digital configuration to the pin. In certain implementations, the IC includes multiple pins, and the digital configuration is based on the impedances detected on each of the pins.

Abstract: Embodiments of the present invention relate to a battery stack controller system. The system may include a plurality of battery cell stages with cell controller systems (as described above with respect to the first embodiment). The system may also include a stack controller to send charge/discharge commands to the battery stack via a communication network. The stack controller may send the commands to the battery stack based on the requirements of a load or the state of the battery cell stages. The battery cell stages may either comply with the commands or send the commands to neighboring cells via the communication network.

Abstract: Embodiments of the present invention are directed to a battery stack with a leapfrogging communication network. Each cell stage may include a controller, a transmitter, and a pair of receivers. The cell stage in the battery stack may be coupled to the closest two preceding battery cell stages in the stack. In this manner, each cell stage may be able to determine if a fault is present in an immediately preceding cell stage in the stack by monitoring the first preceding cell stage and the second preceding cell stage. If discharge/charge commands transmitted by the second preceding cell stage are not reaching the battery cell stage at issue, the controller may determine that there is a fault in the first preceding cell stage and discharge/charge the cell stage based on the commands transmitted by the second preceding cell stage.

Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

Abstract: Embodiments of the present invention are directed to improved battery packaging designs. The battery pack design may include a battery cell, a plurality of transistors, and a controller. The transistors may be coupled to the terminals of the battery cell in an H-bridge configuration. The controller may control the transistors to bypass the battery cell based on the current flowing between the output terminals of the battery pack. In such a manner, the controller may prevent damage to the battery cell and improve the overall safety of the battery pack in hazardous conditions. Moreover, the design may allow for more efficient charging/discharging of the cells that are most ready to accept/supply current.

Abstract: Embodiments of the present invention are directed to an improved battery packaging design. The battery pack design may include a battery cell, a plurality of transistors, and a controller. The transistors may be coupled to the terminals of the battery cell in an H-bridge configuration. The controller may control the transistors to bypass the battery cell based on the current flowing between the output terminals of the battery pack. In such a manner, the controller may prevent damage to the battery cell and improve the overall safety of the battery pack in hazardous conditions.

Abstract: A driver may provide a transition of a switch between an on state and an off state in two stages. In the first stage, the voltage slew rate of the voltage at an output terminal of the switch may be controlled. In the second stage, the current gradient of the switch may be controlled. The transition between the first stage and the second stage may be made based on the value of the voltage at the output terminal of the switch.

Abstract: A MEMS switch device including: a substrate layer; an insulating layer formed over the substrate layer; and a MEMS switch module having a plurality of contacts formed on the surface of the insulating layer, wherein the insulating layer includes a number of conductive pathways formed within the insulating layer, the conductive pathways being configured to interconnect selected contacts of the MEMS switch module.

Abstract: An electrical circuit includes a comparator that receives a first signal at a first input pin, where the first signal is indicative of a current drawn from a power supply unit (PSU) that delivers power to an electronic component. The comparator substantially simultaneously receives a second signal at a second input pin, where the second signal is indicative of a voltage provided by the PSU to the electronic component and is set to a predetermined threshold. An output of the comparator changes if a difference exists between the first signal and the second signal. The electrical circuit includes a variable gain amplifier that provides the first signal to the comparator, where a gain of the variable gain amplifier is set according to the predetermined threshold.

Abstract: In one example, there is disclosed a hybrid analog-digital point-of-load controller (ADPOL) for use in a power supply. The ADPOL is configured to respond to transient current loads. In the presence of moderate current transients, power is clocked by a digital power core, which may be programmatically configured to adjust pulse width in response to the transient. In the presence of larger current transients, control may be passed to an analog transient compensator, which includes high-speed circuitry selecting between a very high-duty-cycle clock and a very low-duty-cycle clock, which will drive the transient back to the digital control domain.

Abstract: Electronic circuitry comprising operational circuits of active switching type requiring timing signals, and conductive means for distributing said timing signals to the operational circuits, wherein the timing signal distribution means includes a signal path that has different phases of a drive signal are supplied via active means at different positions about the signal path where that path exhibits endless electro-magnetic continuity without signal phase inversion or has interconnections with another signal path having different substantially unidirectional signal flow where there is no endless electromagnetic continuity between those signal paths and generally has non-linear associated circuit means where the signal path is of a transmission line nature.

Abstract: A method for calibrating a clock and data recovery circuit may include configuring a phase detector as a bang-bang phase detector. The bang-bang phase detector may be used to determine a phase difference between a sampling clock provided by an interpolator and a calibration signal. The phase detector may also be configured as a linear phase detector. While using the linear phase detector, a linear phase detector parameter may be adjusted such that the phase difference between the calibration signal and the sampling clock is zero, while keeping the phase of the sampling clock fixed.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: Packages and methods for 3D integration are disclosed. In various embodiments, a first integrated device die having a hole is attached to a package substrate. A second integrated device die can be stacked on top of the first integrated device die. At least a portion of the second integrated device die can extend into the hole of the first integrated device die. By stacking the two dies such that the portion of the second integrated device die extends into the hole, the overall package height can advantageously be reduced.