Abstract: The present disclosure describes an improved multi-stage noise shaping (MASH) analog-to-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (??) modulator is provided at the front-end of the MASH ADC, and another full ?? modulator is provided at the back-end of the MASH ADC. The front-end ?? modulator digitizes an analog input signal, and the back-end ?? modulator digitizes an error between the output of the front-end ?? modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.

Abstract: A circuit may include a plurality of primary digital-to-analog (DAC) elements for converting a digital input signal into an analog output signal. A control circuit may control each primary DAC element to switch between a first state and a second state based on the digital input signal to provide the analog output signal at an output representing the digital input signal. A plurality of corrective DAC elements may be coupled in parallel to the plurality of primary DAC elements between the control circuit and the output. The plurality of corrective DAC elements may be controlled to mitigate for intersymbol interference (ISI) due to parasitic capacitance in the primary DAC elements. The plurality of corrective DAC elements may not contribute a direct current to the analog output signal.

Abstract: A method of forming a junction field effect transistor, the transistor comprising: a back gate; a channel; a top gate; a drain and a source in current flow with the channel; wherein the method comprises selecting a first channel dimension between the top gate and the back gate such that a significant current flow path in the channel occurs in a region of relatively low electric field strength.

Abstract: An inductive device may include a pair of half-shell magnetically-conductive housings joined together and defining an enclosed cavity between them. The inductive device may also include primary and secondary windings provided spatially within the cavity providing magnetic coupling between them. The windings may be electrically insulated from each other and terminals of the primary and secondary windings may traverse to an exterior of the inductive device.

Abstract: A mixer includes an input stage to convert an RF input signal to an output signal, and a mixer core to mix the output signal from the input stage with a local oscillator signal. The input stage may include an input cell having a first differential pair of cross-connected transistors, and a linearizer coupled to the input cell. The linearizer may include a second differential pair of transistors having first and second inputs coupled to the input terminals and first and second outputs coupled to the output terminals.

Abstract: A method of detecting activity with a MEMS accelerometer stores a value of acceleration, then measures acceleration at a later time, calculates a change in acceleration using the measured acceleration and the stored acceleration, and compares the change in acceleration to an activity threshold to detect activity. A method of detecting inactivity uses a similar technique along with a timer. The method of detecting inactivity with a MEMS accelerometer stores an acceleration value, then measures acceleration at a later time, calculates a change in acceleration using the measured acceleration and the stored acceleration, and compares the change in acceleration to an inactivity threshold. If the change in acceleration is less than the inactivity threshold and, if a predetermined period of time has elapsed, then inactivity is detected.

Abstract: Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply.

Abstract: Apparatus and methods for monolithic data conversion interface protection are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power high supply node, a second SCR and a second diode for providing protection between the signal node and a power low supply node, and a third SCR and a third diode for providing protection between the power high supply node and the power low supply node. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. Configuring the protection device in this manner enables in-suit input/output interface protection using a single cell. The protection device is suitable for monolithic data conversion interface protection in sub 3V operation.

Abstract: A MEMS apparatus has a substrate, a cap forming first and second chambers with the base, and movable microstructure within the first and second chambers. To control pressures, the MEMS apparatus also has a first outgas structure within the first chamber. The first outgas structure produces a first pressure within the first chamber, which is isolated from the second chamber, which, like the first chamber, has a second pressure. The first pressure is different from that in the second pressure (e.g., a higher pressure or lower pressure).

Abstract: A digital-to-analog converter (DAC) comprising a first section having a first plurality of current flow paths forming binary weighted values in the DAC; and a second section connected to the first section and having a second plurality of current flow paths, wherein each of the first and second plurality of current flow paths are switchable between first and second nodes, and wherein weights of one or more of the second plurality of current flow paths are notionally equal to weights of one or more of the first plurality of current flow paths so as to provide redundancy in the first section.

Abstract: In one example embodiment, a programmable filter is provided, including a plurality of variable-inductance networks and a plurality of variable-capacitance networks. The programmable filter may be implemented in a classical filter topology, with variable-capacitance networks replacing discrete capacitors and variable-inductance networks replacing discrete inductors. An example variable-inductance network comprises a primary inductor with an intermediate tap, and secondary inductor connected at the intermediate tap, with switches for selecting an inductance.

Abstract: Systems and methods for amplitude compressing a digital signal. An input signal is divided into frames having a first and second sets of samples. The samples in the second set are also in a subsequent frame. Peak values are determined for the first and second sets. One or more slopes are calculated based on the peak values. The slopes are used to define a scale factor which is applied to the first set to produce the output signal. For example, if the first peak value exceeds an amplitude threshold, first and last samples in the first set to exceed the amplitude threshold are found. Slopes are calculated for each of three regions of the first set demarcated by the first and last samples. In each region a slope is selected. These slopes along with an initial scale factor are used to calculate the scale factor.

Abstract: A multiplexing circuit comprising an converter for converting an input voltage signal to an input current signal. A plurality of first current mirrors for mirroring the input current signal. A switching unit selectively switches each first current mirror to a corresponding output.

Abstract: The invention may provide a receiver including a front-end block to provide a front-end gain on a radio-frequency input signal. The front-end block may include a mixer to convert the radio-frequency input signal to a baseband signal. The receiver also may include a wide-band peak detector coupled to the front-end block and a baseband block to provide a baseband gain on the baseband signal. An analog-to-digital converter may convert the baseband signal to a digital signal. The receiver may further include narrow-band peak detector coupled to an output of the analog-to-digital converter. An automatic gain control circuit may independently control the front-end gain and the baseband gain based on outputs from the wide-band peak detector and narrowband peak detector.

Abstract: A radio frequency diode detector has a set of diodes having a differential voltage output, and a current source electrically coupled to the ring of diodes, the current source coupled to provide a forward bias current. This is followed by nonlinear signal processing to create an overall linear detector suitable for use in microwave power measurement.

Abstract: A multi-level amplifier including a converter circuit being supplied with a supply voltage and operable to generate at least two output voltages, a voltage comparator circuit adapted to compare each of the output voltages with the supply voltage to generate a driving signal, and an amplifier circuit being supplied with an analog input signal, the amplifier circuit including an analog-to-digital converter coupled to a power stage driver and power stage, wherein the power stage driver receives the driving signal from the voltage comparator.

Abstract: Embodiments of the present invention may provide accuracy enhancement techniques to improve ADC SNRs. For example, regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word and extra bit trials may be performed. The results of the regular and extra bit trials may be combined to generate a digital output signal. A residue error may be measured, and the digital output signal may be adjusted based on the measured residue error.

Abstract: An amplifier may include a predistorter receiving an input signal to generate a predistortion signal, a first converter receiving the predistortion signal to generate a preamplified signal, a power amplifier receiving the preamplified signal to generate an output signal based on the preamplified signal and the input signal, and a second converter sampling the output signal to generate a feedback signal. The predistorter may separately and independently generate a predistortion signal component for the in-phase input signal and a predistortion signal component for the quadrature input signal.

Abstract: A switching regulator and control method for the same. The switching regulator employs a hybrid mode. A ramp voltage signal is added to the current sense signal to make the ramp voltage signal overtake the current information when the duty cycle becomes low.

Abstract: A fully on-chip clock generator on an integrated circuit (“IC”) includes a frequency detector for receiving a reference current and providing a first voltage; an error integrator for receiving the first voltage from the frequency detector, comparing it with a reference voltage, and providing a control voltage; a voltage controlled oscillator (“VCO”) for receiving the control voltage from the error integrator, and providing an output clock; and a logic controller on the IC, coupled between the VCO and the frequency detector, and generating logic control signals for controlling the frequency detector. The fully on-chip clock generator requires no external crystal, but its power consumption is significantly lower than a relaxation oscillator that generates the same clock frequency.